Design IP round #2: after road-test, time for the race
Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider - Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung or Intel) was unacceptable. This was the picture in 2010: Synopsys leader on every Interface IP segment, Cadence leader in Verification IP, but only in VIP, and many small IP vendors acting like an electron cloud around Synopsys atom… Moreover, the market value of design IP was 5X the VIP market value, and this is still the case!
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
Latest Blogs
- PCIe Low-Power Validation Challenges and Potential Solutions (PIPE/L1 Substates)
- Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard
- Tidying Up: FIPS-Compliant Secure Zeroization for OTP
- Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP
- Why What Where DIFI and the new version 1.3