Design IP round #2: after road-test, time for the race
May 10, 2013
Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider - Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung or Intel) was unacceptable. This was the picture in 2010: Synopsys leader on every Interface IP segment, Cadence leader in Verification IP, but only in VIP, and many small IP vendors acting like an electron cloud around Synopsys atom… Moreover, the market value of design IP was 5X the VIP market value, and this is still the case!
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success