Early, Accurate, and Faster Exploration and Debug of Worst-Case Design Failures with ML-Based Spectre FMC Analysis

By _Cadence Blog

June 9, 2023

Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. However, using smaller transistors increases complexity and poses many challenges for IC design engineers. At advanced nodes, it is very challenging to ensure a high yield due to large process variations. Primarily, yield helps to determine profitability and shows a clear picture of the quality, so it plays a critical role in semiconductor manufacturing. The purpose of aggressive process scaling is only met if a high yield is ensured and verified. IC designers use Monte Carlo (MC) simulations to find the worst-case design failures and estimate the yield before mass production. This method attains accuracy at the cost of long run-time for analog simulations. With the shrinking time-to-market windows, can we afford to run millions or even billions of statistical simulations and spend so much time on verification?

Cadence Spectre FMC analysis uses machine learning (ML) and advanced statistical techniques to enable early, accurate, and significantly faster yield estimation than traditional brute-force Monte Carlo simulations.

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