Analog design automation: Pipe dream or inevitability?
To start, I am not a career analog design engineer. I have worked for years as an analog/RF design engineer, including a stint in analog/mixed-signal IC design and layout. I also studied control systems and machine learning (ML) pretty deeply for several years, and since then, I have kept marginally well up to date with the data science. These days, I do a good bit of consulting, RF contract design, and a lot of engineering writing. Hence, I am daily reading and researching various engineering, physics, and materials science topics that pertain to electronics, mostly RF and analog. What I am not doing daily is bludgeoning transistors into submission, running sims until my eyes bleed, or playing tetris in a layout editor to wrangle parasitics that are determined to make me look like a fool.
This is why I defer to our esteemed analog design engineer audience on the nuances and vagaries of analog. However, I do have thoughts every now and again. Today, I am having thoughts about a few different blogs and articles I have read about automating analog design. The blogs and articles I have read are mostly from electronic design automation (EDA) software companies. In these written works, I notice a general theme that whoever is writing them seems to believe that analog design, at least in a somewhat significant way, can be automated. I found these claims puzzling for a few different reasons.
To read the full article, click here
Related Semiconductor IP
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
- JESD204E Controller IP
Related Blogs
- Analog Design and Layout Migration automation in the AI era
- Analog Design vs. Automation -- Why Are They At Odds?
- Build or Buy? The Design Rules Remain the Same
- Processor design automation to drive innovation and foster differentiation
Latest Blogs
- The Memory Imperative for Next-Generation AI Accelerator SoCs
- Leadership in CAN XL strengthens Bosch’s position in vehicle communication
- Validating UPLI Protocol Across Topologies with Cadence UALink VIP
- Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology
- LPDDR6 vs. LPDDR5 and LPDDR5X: What’s the Difference?