Accellera + OSCI = what exactly?
At this point, everyone has reported on the merger of OSCI and Accellera, two standards groups that operate in the EDA and IP domain. The principle output from OSCI has been the SystemC language and technologies surrounding it, such as the TLM 2.0 transaction level modeling interface. Accellera has been in existence a lot longer and is the home of several languages such as Verilog, SystemVerilog, PSL and some aspects of VHDL. More recently it has become the home for verification methodologies such UVM and, through its merger with the SPIRIT consortium, got into the area of IP description and management. So what are the advantages and disadvantages of having these come together under one roof?
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Parameterizable compact BCH codec
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
Related Blogs
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- The Perfect Solution for Local AI
- Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
Latest Blogs
- Physical AI at the Edge: A New Chapter in Device Intelligence
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7