Accellera + OSCI = what exactly?
At this point, everyone has reported on the merger of OSCI and Accellera, two standards groups that operate in the EDA and IP domain. The principle output from OSCI has been the SystemC language and technologies surrounding it, such as the TLM 2.0 transaction level modeling interface. Accellera has been in existence a lot longer and is the home of several languages such as Verilog, SystemVerilog, PSL and some aspects of VHDL. More recently it has become the home for verification methodologies such UVM and, through its merger with the SPIRIT consortium, got into the area of IP description and management. So what are the advantages and disadvantages of having these come together under one roof?
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- The Shift-Left Approach to Software Development
- Moving the World with MIPS M8500 Real-Time Compute Solutions
- Real-Time Intelligence for Physical AI at the Edge
- Introducing MIPS Sense data movement engines
Latest Blogs
- Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
- Why Hardware Security Is Just as Critical as Software Security in Modern Systems
- How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors