Accelerating EDA innovation through SoC design methodology convergence
According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
To read the full article, click here
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related Blogs
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- Consolidation and EDA innovation
- SoC verification through Managed service
- SOC Design Techniques that Enable Autonomous Vehicles
Latest Blogs
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development