A Tale of Two Approaches to High-Performance IoT
Extensible Processors vs Accelerators – and how RISC-V changes the dynamic
If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload complex processing from the main cores. This solution should give the best power and performance outcome.
The accelerators are usually implemented as standalone RTL blocks connected to the main processor bus, and are optimized to be very efficient on the data types they work with. So on the surface they appear to be the logical choice to deliver optimal power and performance.
BUT, how did this common architecture come about, and is it always the best approach?
To read the full article, click here
Related Blogs
- Ambient IoT: 5 Ways Packetcraft's Software is Optimized to Enable the New Class of Connectivity
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- Intel's Tale of Two Cities
- CEVA DSPs and the Tale of Two Chip Underdogs from China
Latest Blogs
- The Evolution of AI and ML- Enhanced Advanced Driver Systems
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison