A Striped Bus Architecture for Minimizing Multi-Core Interference
Understanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture might seem straightforward, the landscape becomes notably more complex when dealing with multiple cores. Here, contention for shared resources such as caches, buses, and peripherals add layers of uncertainty to the timing analysis. In this blog post we describe the on-chip bus architecture of the GR765 octa-core LEON/RISC-V microprocessor. This infrastructure is designed to improve the system performance, minimize multi-core interference, and simplify the worst-case execution time analysis.
Interference Challenges
The architecture of many modern multi-core microprocessors imposes some key challenges:
- Bandwidth: Cores competing for simultaneous access to shared resources may result in bottlenecks, leading to delays or inefficiencies in resource utilization.
- Quality of Service (QoS) Management: Ensuring fair and predictable access to the bus for diverse software instances with varying criticality proves challenging.
These constraints are particularly critical in scenarios where exceeding execution time thresholds could trigger failures. Consequently, software developers must carefully consider these limitations to ensure that their applications behave as intended. Moreover, accommodating these constraints often entails longer development cycles and substantial performance trade-offs.
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