When will you be facing these 28nm design challenges?
October 11, 2010
It’s been shocking and exhilarating to see all of the 28nm process announcements lately. If you throw them all into a basket, you might get the idea that nothing could be simpler than throwing together a 28nm design with hundreds of millions of gates. A tag team consisting of JC Parker and Vishwas Rao set a standing-room-only audience straight about that topic at this week’s LSI 2010 Conference and Showcase. Their presentation was titled “MegaChip Design: Accelerated Closure of 100+ Million Gate Designs.” Parker is LSI’s Director of Design Implementation and Rao is a Senior Manager of Design Closure Methodology. With titles like those, and from the presentation, you can tell these two have seen their share of design challenges.
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