IP Catalog > XSPI

xSPI IP

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Compare 12 IP from 7 vendors (1 - 10)
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • XSPI Controller IP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
  • xSPI Master IP | NOR IP
    • JESD 251 compliant
    • JEDEC SFDP Compliant
    Block Diagram -- xSPI Master IP | NOR IP
  • xSPI NOR Flash controller
    • Memory mapped access to the connected flash devices
    • Continuous Burst transfer support
    • Auto boot support
    Block Diagram -- xSPI NOR Flash controller
  • xSPI Flash Memory Controller
    • Compatible to most SPI protocols used by the NOR-Flash vendors including xSPI (JEDEC’s JESD251), and Xccela
    • Single, Dual, Quad, Twin-Quad and Octal SPI lanes. Single and Dual Transfer Rate (STR and DTR)
    • Programmable bit-length and number of SPI lanes used for command, address, latency (dummy cycle) and data. Programmable command encoding
    • XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
    Block Diagram -- xSPI Flash Memory Controller
  • SafeSPI Controller
    • Compliant to SafeSPI Rev 2.0.
    • Master, slave, or monitor roles
    • All frame formats
    • Slave selection options
    Block Diagram -- SafeSPI Controller
  • FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
    • Set of software accessible control registers to
    • execute any Flash memory command
    • Support for most popular SPI like FLASH memories and PSRAM
    • Supports any device clock frequency, polarity and phase
  • Serial Flash Controller IP
    • Compliant with Flash Devices from major Flash Device Vendors
    • Full SPI Master Functionality.
    • Supports Single, Dual, Quad, Octal SPI data widths SOC Master and SOC Slave bus can be APB/AHB/AXI/OCP/Tilelink/Wishbone/VCI/PLB/Avalon or any other protocol listed above.
    • Supports 3 modes of operation
  • AHB Subsystem
    • Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as: BA2x, ARM Cortex-M0/M1M3/M4, and Several RISC-V processors
    • AHB-SBS-BASE integrates: AHB Multi-Layer Interconnect, xSPI Controller, SRAM Controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
    • AHB-SBS-EXT adds: Multichannel DMA, SPI-to-AHB bridge, and External parallel flash or SRAM controller
    • Highly configurable and customizable
    Block Diagram -- AHB Subsystem
  • SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
    • Set of software accessible control registers to execute any Flash memory command
    • Supports any device clock frequency, polarity and phase,
    • Programmable baud rate generator,
    • Built in FLASH Commands decoder supports most popular FLASH devices,
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