IP Catalog > XSPI

xSPI IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (25)
Compare 25 IP from 13 vendors (1 - 10)
  • xSPI Multiple Bus Memory Controller
    • SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
    • JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.
    Block Diagram -- xSPI Multiple Bus Memory Controller
  • xSPI Verification IP
    • xSPI Verification IP provides verification of xSPI (Extended SPI) for devices using the Serial Parallel Interface (SPI) protocol for master and slave modes.
    • It is a reusable, configurable, pre-verified, and plug-and-play verification component developed in System Verilog.
  • Expanded Serial Peripheral Interface (xSPI) Slave Controller
    • The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
    • It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI) Slave Controller
  • Expanded Serial Peripheral Interface (xSPI)Master Controller
    • The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI)Master Controller
  • Simulation VIP for xSPI
    • xSPI Profile 1
    • SPI (Read Zero Latency), DUAL (1-1-2, 1-2-2), Quad (As per JESD251-A1), and Octal modes Data Rate: STR and DTR
    • Modes
    • SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes
    Block Diagram -- Simulation VIP for xSPI
  • xSPI (Expanded Serial Peripheral Interface) Verification IP
    • Follows xSPI basic specification as defined in JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices.
    • Fully compatible with JESD251 and JESD251-1 standards.
    • Support Master and Slave Mode.
    • Supports 4-wire, 7-wire, 8-wire, 11-wire and 12-wire interfaces.
    Block Diagram -- xSPI (Expanded Serial Peripheral Interface) Verification IP
  • XSPI (Expanded Serial Peripheral Interface) Synthesizable Transactor
    • Follows XSPI basic specification as defined in JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices
    • Supports Master and Slave Mode
    • Supports 4-wire,7-wire,11-wire interface
    • Supports data width upto 8 bits
    Block Diagram -- XSPI (Expanded Serial Peripheral Interface) Synthesizable Transactor
  • XSPI Master IIP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
    Block Diagram -- XSPI Master IIP
  • XSPI Controller IIP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
    Block Diagram -- XSPI Controller IIP
  • Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
    • Flexibility: Multiple SPI protocol support within single IP
    • Simplicity: PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing
    • High Performance: Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)
×
Semiconductor IP