xSPI (Expanded Serial Peripheral Interface) Verification IP

Overview

xSPI (Expanded Serial Peripheral Interface) is the serial synchronous communication protocol developed by JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices.It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

xSPI (Expanded Serial Peripheral Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

xSPI (Expanded Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows xSPI basic specification as defined in JEDEC eXpanded Serial Peripheral Interface (xSPI)for Non Volatile Memory Devices.
Fully compatible with JESD251 and JESD251-1 standards.
Support Master and Slave Mode.
Supports 4-wire, 7-wire, 8-wire, 11-wire and 12-wire interfaces.
Supports data width upto 8 bits.
Supports baud rate selection.
Supports internal clock division check.
Supports Clock Polarity (CPOL) and Clock Phase (CPHA) selections.
Supports single and burst transfer mode.
Supports following IO protocol modes

24 bit and 32 bit addressing
Data rate options for SDR and DDR

Supports following slave reset options

Power-on Reset
In-band Reset
Separate Reset Signal

Supports power management option

Deep Power Down (DPD) enter and exit commands

Supports flexible erase operation like,

4KByte sector erase
8KByte block erase
32KByte block erase
64KByte block erase

Supports Write protection mode.
Supports constraints Randomization.
Supports backdoor initialization of data.
Built in functional coverage analysis.
Status counters for various events on bus.
Supports single,dual,quad mode and Octal bus width operation.
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on xSPI bus.
xSPI Slave can be configured as standard device or can use FIFO for data passing.
Master contains rich set of commands for both standard device and FIFO model mode.

Benefits

Faster testbench development and more complete verification of xSPI designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the xSPI testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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