Ultra Ethernet IP
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174
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15
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Ultra Ethernet Verification IP
- The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
- The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
- This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
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100G MAC/PCS Ultra Ethernet
- The IP integrates MAC Layer, RS Sub-Layer and 100G PCS Base-R cores according to IEEE 802.3 standard to provide seamless connection between an application and serdes interfaces
- 128-bit interface for TX and RX between MAC and the application Serdes interface – configurable to support PAM2 and PAM 4
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Complete 1.6T Ultra Ethernet IP Solution
- Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
- Supports evolving IEEE 802.3 and OIF-224G electrical standards
- Provides support for 4 x 400G, 2 x 800G, and 1.6T Ethernet rates using 112Gbps and 224Gbps SerDes
- Meets performance criteria for chip-to-chip, chip-to-module, and long reach copper/backplane interconnects
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10G Ultra Low Latency Ethernet Solution
- Ultra low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode)
- Ultra low latency 10GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns
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25G Ultra Low latency, 64-bit Ethernet MAC + PCS Solution (64-bit and 128-bit UI)
- MAC Core Features
- PCS Core Features
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1-56Gbps Serdes - 7nm (Ultra Low Latency)
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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Low-Latency IP 10G Ethernet MAC
- LeWiz MAC tracks the Ethernet line for link detection
- On the receiving side, it:
- On the transmit side, it:
- Driver Support is available for Linux (Windows and others available based on customer request)
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10/100 Ethernet PHY for TSMC 22nm ULP
- TSMC 22nm ULP
- support EEE
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Ultra Low Latency 10G TCP Endpoint
- The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
- It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.
