Ethernet MAC & PCS
100G Ethernet MAC and PCS have been stable and adopted in the market for many years and used extensively in ethernet transport for home, industrial and data center markets.
Recent requirements driven by AI training and inference driving more stringent latency and link management are now being developed.
Ultra Ethernet is a new upcoming standard being adopted to improve AI support to reduce tail latency and improve overall system level performance, congestion and overall management.
The Ultra MAC can be licensed with Ultra Ethernet Support.
Low Power& latency
Generally, solutions in the market are not optimized for lower latency or low gate count (hence lower power).
The Ultra MAC is architected for lowest latency and size/power. It is designed to support both 25G NRZ PAM 2 PHY as well as 106G PAM 4 PHY and multiple FEC options.
Key advantage of NRZ PHY is it is possible use without FEC, making it ideal for clustering CPU & edge AI applications.
For lowest latency – the recovered clock is used for MAC/PCS operation for both versions.
Todays AI and edge applications require lowest latency & power.
Ultra Ethernet
This IP supports insertion and deriving Control Ordered Set (CtlOS). The Control Ordered Set (CtlOS) is a message mechanism utilized by the UEC Link Layer which features Credit-Based Flow Control (CBFC) and LinkLevel Retry (LLR). This IP generates CtlOS on transmit side based on the data provided by the application over a dedicated interface.
On the receive side the IP derives the CtlOS from the incoming traffic and delivers the payload data to the application over the dedicated interface.
This IP is designed to work with upper link layers to enable designers to build a low power low latency Ultra Ethernet link.
