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"keyfeatures " => "<ul><li>Compliant with the JEDEC UFS v3.1</li><li>Backward compatibility JEDEC UFS v3.0 & v2.1</li><li>TAG overlap/LBA overlap/Valid UPIU check</li><li>Maximum DATA OUT = 64KB</li><li>Maximum DATA IN = 64KB</li><li>Maximum RTT number= 8</li><li>CMD Queue Depth = 32</li><li>HW Auto NOP IN Response</li><li>HW Auto Query Response</li><li>HW Auto Write Function</li><li>Support HPB v1.0 (Host-aware Performance Booster)</li><li>Support EHS (Extra Header Segment)</li></ul> "
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Verification :<br />\n
IP Functionally is verified in NC – Verilog simulation software using test bench written in Verilog HDL
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通用闪存（UFS）控制器IP符合最新的JEDEC UFS v3.1规范。UFS是高性能、低功耗的串行接口，可以有效地在主机处理器和大容量存储设备之间移动数据。<br />\r\n
客户的产品设计师能够用UFS控制器IP与内部开发的UniPro控制器IP和M-PHY IP轻松地集成PHY和控制器，并通过UFS IP解决方案加快产品的上市时间.<br />\r\n
验证：使用Verilog HDL编写的测试台在NC-Verilog模拟软件中进行功能验证
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Verification :\n
IP Functionally verified in NC – Verilog simulation software using test bench written HDL Compliant v3.1Backward compatibility v3.0 & v2.1TAG overlap/LBA overlap/Valid UPIU checkMaximum DATA OUT = 64KBMaximum IN RTT number= 8CMD Queue Depth 32HW Auto NOP ResponseHW Query Write FunctionSupport HPB v1.0 (Host-aware Performance Booster)Support EHS (Extra Header Segment)
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Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
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UFS是一种高性能串行接口，用于移动系统中，帮助主机处理器与闪存和其他非易失性存储器等大容量存储设备进行通信。这种通信是通过UFS主机实现的，使用MIPI UniPro作为链路和PHY层的PHY。UFS主机控制器接口负责管理主机软件与UFS设备之间的通信，用于数据传输。它还执行接口管理和电源管理/控制过程。我们的UFS主机可以与任何UFS设备无缝协作，配合MIPI UniPro和MPHY使用。此外，我们还提供包括软件和验证平台在内的完整解决方案。可配置选项包括：<br />\r\n
C端口<br />\r\n
符合UFS规范v2.1并且向后兼容<br />\r\n
AXI支持
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UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Host using MIPI UniPro as Link PHY for layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Device along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v2.1 backward compatible tAXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingPriority arbitration UPIUs index-based processing within Command Query UPIUsSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 2.1 UFS Host Device MIPI MPHY Unipro 3.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove "
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"keyfeatures " => "<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li><li>AXI support</li><li>All UPIU processing</li><li>Data-in, data-out, command, response, RTT, query, task management and reject</li><li>Complete control of UIC Layer by UFS Host</li><li>Error reporting and handling</li><li>Support for 32 UTP transfer request descriptors and 8 UTP task management descriptors for UFS host</li><li>Support for Boot LUN, RPMB, and well-known LUNs</li><li>Device: Up to 8 LUNs configurable; up to 8 command queues in each LUN; up to 8 tasks handling for task management</li><li>Priority LUN handling</li><li>Security features</li></ul> "
"keyfeatures_cn " => "<ul><li>符合UFSv3.1规范，并向后兼容UFS v3.0和v2.1规范\r </li><li>支持AXI\r </li><li>支持所有UPIU处理\r </li><li>数据导入、数据输出、命令、响应、RTT、查询、任务管理和拒绝\r </li><li>由UFS主机完全控制UIC层\r </li><li>错误报告和处理\r </li><li>支持针对UFS主机的32个UTP传输请求描述符和8个UTP任务管理描述符\r </li><li>支持引导LUN、RPMB和著名的LUN\r </li><li>设备：最多可配置8个LUN；每个LUN中最多可配置8个命令队列；针对任务管理的最多8个任务处理\r </li><li>优先级LUN处理\r </li><li>安全功能</li></ul> "
"keywords " => "Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 3.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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"overview " => """
UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via UFS Device, using MIPI UniPro as Link and MPHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Device works seamlessly with any UFS Host, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.<br />\n
Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
"overview_cn " => """
UFS是用于主机处理器和大容量存储设备移动系统的高性能串行接口，如闪存和其他非易失性存储设备之间的通信。这种通信是通过UFS设备实现的，使用MIPI UniPro作为Link和MPHY作为PHY层。这种通信是通过UFS设备实现的，使用MIPI UniPro作为链接，MPHY作为PHY层。UFS主机控制器接口负责管理数据传输所需的主机软件和UFS设备之间的通信。它还执行接口管理和电源管理/控制过程。我们的UFS设备可以与任何UFS主机以及MIPI UniPro和MPHY无缝工作。这个IP的交付件可选择<br />\r\n
• C端口<br />\r\n
• 应用程序接口-APB或AXI :
"""
"partnumber " => "MIPI UFS v3.1 Device Controller IP "
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"provider.name " => "T2M GmbH "
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"provider.priority " => 2001
"provider.slug " => "t2m-gmbh "
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"seofeatures " => """
<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li>\n
<li>AXI support</li>\n
<li>All UPIU processing</li>\n
<li>Data-in, data-out, command, response, RTT, query, task management and reject</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro "
"shortdescription_cn " => "MIPI UFS v3.1 设备控制器IP，兼容M-PHY和Unipro "
"slug " => "mipi-ufs-v3-1-device-controller-ip-compatible-with-m-phy-and-unipro "
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"text_high_priority " => "MIPI UFS v3.1 Device Controller IP Compatible with M-PHY and Unipro T2M GmbH "
"text_low_priority " => """
UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Device using MIPI UniPro as Link MPHY for PHY layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Host along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v3.1 backward compatible v3.0 & v2.1AXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsDevice: Up LUNs configurable; up queues each LUN; tasks handling managementPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 3.1 UFS Host Device MIPI MPHY Unipro 3.0 2.1 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove proven "
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"keyfeatures " => "<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li><li>Programmable 1, 2, or 4 data lanes</li><li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li><li>Support for end-to-end flow control</li><li>Support for all traffic classes</li><li>Support for preemption of high-priority frames</li><li>Support for up to 32 C-Ports</li><li>Round Robin arbitration across C-Ports</li><li>Group acknowledgement of up to 16 frames per traffic class</li><li>Support for frame retransmission</li><li>Configurable buffer spaces</li><li>CSD, CSV support</li><li>Support for UniPro test feature</li><li>TMPI support</li><li>Efficient power management</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro标准V1.6标准和MPHY标准3.x标准\r </li><li>可编程的1、2或4个数据通道\r </li><li>支持M-PHY HS数据速率HS-Gear-1、Gear-2、Gear-3、A/B模式和PWM数据速率PWM-G1到PWM-G7\r </li><li>支持端到端流量控制\r </li><li>支持所有流量类\r </li><li>支持高优先级帧的抢占\r </li><li>支持多达32个c端口\r </li><li>跨c端口的循环仲裁\r </li><li>每个流量类最多16帧的组确认\r </li><li>框架重传支架\r </li><li>可配置缓冲区空间\r </li><li>CSD、CSV支持\r </li><li>支持UniPro测试功能\r </li><li>TMPI支持\r </li><li>高效的电源管理</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
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"logo2 " => "t2m-v2-66bb477f994ef.webp "
"name " => "asic.node "
"overview " => """
UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobile device. UniPro allows device components to utilize MIPI PHY layer to communicate and exchange data with devices on the other side of MIPI lanes. UniPro supports a wide range of device applications like application processor, camera controller, display controllers, and storage controllers like UFS or memory (RAM) controllers.<br />\n
Our MIPI UniPro is designed to be PHY-agnostic, supporting a wide range of applications simultaneously in the application layer. Our MIPI UniPro along with other application solutions like CSI-3 or UFS and MPHY offers an comprehensive solution
"""
"overview_cn " => "UniPro是由MIPI联盟定义的一种分层协议，用于连接移动设备内的设备和组件。UniPro允许设备组件利用MIPI物理层与MIPI通道另一端的设备进行通信和数据交换。UniPro支持广泛的设备应用，如应用处理器、相机控制器、显示控制器和存储控制器（如UFS或内存（RAM）控制器）。我们的MIPI UniPro设计为不依赖于PHY，能够在应用层同时支持广泛的应用。我们的MIPI UniPro与其他应用解决方案（如CSI-3或UFS）和MPHY一起提供了一个全面的解决方案。 "
"partnumber " => "MIPI Unipro v1.6 Controller IP "
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"provider.name " => "T2M GmbH "
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<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li>\n
<li>Programmable 1, 2, or 4 data lanes</li>\n
<li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li>\n
<li>Support for end-to-end flow control</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.6 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-6-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.6 Controller IP Compatible with M-PHY and UFS T2M GmbH "
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UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within mobile device. allows device to utilize PHY layer communicate exchange data with on other side of lanes. supports wide range applications like application processor camera controller display controllers storage UFS or memory (RAM) controllers.\n
Our designed be PHY-agnostic supporting simultaneously in layer. Our along solutions CSI-3 MPHY offers an comprehensive solution Compliant Standard V1.6 standard 3.xProgrammable 1 2 4 lanesSupport M-PHY HS rates HS-Gear-1 Gear-2 Gear-3 both A/B modes PWM PWM-G1 PWM-G7Support end-to-end flow controlSupport all traffic classesSupport preemption high-priority framesSupport up 32 C-PortsRound Robin arbitration across C-PortsGroup acknowledgement 16 frames per classSupport frame retransmissionConfigurable buffer spacesCSD CSV supportSupport test featureTMPI supportEfficient power management
"""
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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"keyfeatures " => "<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61 </li><li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute </li><li>Support Asymmetric lanes and Gears </li><li>Support Data Lanes connected 2 lanes </li><li>Support Slow/ Slow-Auto/ Fast/ Fast-Auto mode </li><li>Support PWMG1-G4/HSG1-G4/Rate A/B </li><li>Support Skip symbol insertion </li><li>Support Scramble function </li><li>Support Quality of Service Monitoring (QoS) </li><li>Support PHY test mode & UniPro test feature </li><li>Support Cport0 and TC0 </li><li>Support HW auto LinkStartUp </li><li>Maximum R/W Performance up to 2170MB/s </li><li>UniPro IP Power-Off in Hibernate state</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro v1.8规范，并向后兼容MIPI UniPro v1.61\r </li><li>支持HS-Gear4 M-PHY IP v4.1和对属性的访问\r </li><li>支持不对称的车道和齿轮\r </li><li>支持数据通道，连接了2条通道\r </li><li>支持慢、慢自动、快、快自动模式\r </li><li>支持PWMG1-G4/HSG1-G4/Rate A/B\r </li><li>支持跳过符号插入\r </li><li>支持痉挛功能\r </li><li>支持服务质量监控（QoS）\r </li><li>支持PHY测试模式和UniPro测试功能\r </li><li>支持Cport0和TC0\r </li><li>支持硬件自动链接启动\r </li><li>最大收发性能最高可达2170MB/s\r </li><li>UniPro IP断电</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
"logo " => "t2m-v2-66bb477f994ef.webp "
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"name " => "asic.node "
"overview " => "This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a MIPI M-PHY link. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. When this MIPI UniPro Controller IP is combined with Universal Flash Storage (UFS) Controller IP and also our M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution. "
"overview_cn " => """
MIPI UniPro控制器IP符合最新的MIPI UniPro v1.8规范，提供了通过MIPI M-PHY链接控制UniPro链接的能力。MIPI UniPro是一种高性能、 chip-to-chip、用于移动应用的串行互连总线。<br />\r\n
客户的产品设计师能够吧MIPI UniPro控制器IP与通用闪存（UFS）控制器IP以及M-PHY IP轻松地集成PHY和控制器 IP，降低产品研发风险很低，加快产品上市时间.<br />\r\n
<br />\r\n
"""
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<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61</li>\n
<li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute</li>\n
<li>Support Asymmetric lanes and Gears</li>\n
<li>Support Data Lanes connected 2 lanes</li>\n
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"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.8 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.8 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-8-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.8 Controller IP Compatible with M-PHY and UFS T2M GmbH "
"text_low_priority " => "This MIPI UniPro Controller IP is compliant with the latest v1.8 specification provides capability to control link over a M-PHY link. high-performance chip-to-chip serial interconnect bus for mobile applications. When this combined Universal Flash Storage (UFS) and also our designers can easily integrate PHY controller low risk accelerate time-to market UFS solution. Compliant backward compatible v1.61 Support HS-Gear4 v4.1 access attribute Asymmetric lanes Gears Data Lanes connected 2 Slow/ Slow-Auto/ Fast/ Fast-Auto mode PWMG1-G4/HSG1-G4/Rate A/B Skip symbol insertion Scramble function Quality of Service Monitoring (QoS) test & feature Cport0 TC0 HW auto LinkStartUp Maximum R/W Performance up 2170MB/s Power-Off in Hibernate state "
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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<p>UFS VIP is a comprehensive VIP solution portfolio for SoC and IP designs incorporating the UFS Host Controller (UFSHCI), UFS 4.0, and UME standard, in conjunction with the MIPI Unipro and M-PHY standards.</p>\r\n
\r\n <ul>\r\n
\t <li>UFS host supported two ways:\r\n \t <ul>\r\n \t\t <li>UFSHC 4.0 driver model supports UME 1.0 and implements UFSHCI programming interface, including host adapter to various host bus interfaces, including AMBA AXI and AHB</li>\r\n \t\t <li>Generic host model emulates UFSHC host driver and UFSHCI-based controller</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>UFS device model emulates simple UFS device, including sparse logical block storage and processes over 20 SCSI</li>\r\n \t <li>Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5</li>\r\n \t <li>Supports UFS DME and CPort users</li>\r\n \t <li>CPort adapter interfaces to Avery or third party UniPro IP/VIP, enabling mix and match between UFS and Unipro layers to support module-level integration and verification</li>\r\n \t <li>M-PHY model</li>\r\n \t <li>Support draft M-PHY 5.0 Multiple LANE provisions</li>\r\n \t <li>Multiple transmission modes include LS-MODE NRZ and PWM signaling Multiple power saving modes</li>\r\n \t <li>Support error injections (encoding, disparity, etc.)</li>\r\n \t <li>UniPro model\r\n \t <ul>\r\n \t\t <li>Emulates UniPro draft 2.0 protocol stack layers and M-PHY</li>\r\n \t\t <li>Supports all service primitives (SAP) and service data units (x_SDU)</li>\r\n \t\t <li>DME user supports all sequences of control, configuration, and status primitives</li>\r\n \t\t <li>Transport service</li>\r\n \t\t <li>Allocates connections between CPorts</li>\r\n \t\t <li>Schedules message transfers between CPort users</li>\r\n \t\t <li>Supports CPort signal interface</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Supports UniPro test feature</li>\r\n \t <li>Inject errors at all layers through callbacks</li>\r\n \t <li>Comprehensive assertions track UFS and MIPI compliance coverage</li>\r\n \t <li>Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences</li>\r\n \t <li>Tracker log monitors all levels and improves debug</li>\r\n \t <li>Comprehensive directed and constrained random compliance test suite for UFSHCI and UFS device achieves high protocol coverage</li>\r\n </ul>
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<p><strong>Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PHY</strong></p>\r\n
\r\n <p>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</p>\r\n
\r\n <p>With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work more on verifying both low-level and system-level functions.</p>\r\n
\r\n <p>Avery compliance test suites offer effective core-through-chip-level tests, includ ing those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.</p>
"""
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\t <li>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</li>\r\n </ul>
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Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS UniPro M-PHY\r\n
\r\n Avery UFS/Unipro VIP provides a comprehensive solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation robust packet physical layer controls error injection protocol checks coverage functional analyzer-like features for debugging performance analysis metrics.\r\n
\r\n With the capabilities Avery engineers can work more efficiently develop complex tests on verifying both low-level system-level functions.\r\n
\r\n Avery compliance test suites offer effective core-through-chip-level includ ing those used workshops well extended developed by to cover specification features. is portfolio SoC IP incorporating Host Controller (UFSHCI) 4.0 UME standard conjunction MIPI M-PHY standards.\r\n
\r\n \r\n \t UFS host supported two ways:\r\n \t \r\n \t\t UFSHC driver model supports 1.0 implements UFSHCI programming interface including adapter various bus AMBA AXI AHB\r\n \t\t Generic emulates UFSHC UFSHCI-based controller\r\n \t \r\n \t \r\n \t UFS device simple sparse logical block processes over 20 SCSI\r\n \t Supports command sets: Native SPC-4 SBC-3 SAM-5\r\n \t Supports DME CPort users\r\n \t CPort or third party IP/VIP enabling mix match between layers support module-level integration verification\r\n \t M-PHY model\r\n \t Support draft 5.0 Multiple LANE provisions\r\n \t Multiple transmission modes include LS-MODE NRZ PWM signaling power saving modes\r\n \t Support injections (encoding disparity etc.)\r\n \t UniPro model\r\n \t \r\n \t\t Emulates 2.0 stack M-PHY\r\n \t\t Supports all service primitives (SAP) data units (x_SDU)\r\n \t\t DME user sequences control configuration and status primitives\r\n \t\t Transport service\r\n \t\t Allocates connections CPorts\r\n \t\t Schedules message transfers users\r\n \t\t Supports signal interface\r\n \t \r\n \t \r\n \t Supports feature\r\n \t Inject errors at through callbacks\r\n \t Comprehensive assertions track coverage\r\n \t Functional tracks range FSMs operational sequences\r\n \t Tracker log monitors levels improves debug\r\n \t Comprehensive directed suite achieves high coverage\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>\r\n
\r\n <p> </p>
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<p>The UFS 2.1 Host Stack is a stack developed for UFS Host Controllers that are used to connect to UFS devices via UniPro/M-PHY. The stack can also be used for validating a UFS device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.</p>\r\n
\r\n <p>The modular UFS 2.1 Host Stack is architected to be OS and platform independent which eases porting effort. It has thin OS and hardware abstraction layers making it highly portable.</p>\r\n
\r\n <p>The UFS 2.1 Host Stack has a low-level hardware layer that is purely OS independent and users can use this layer alone for UFS host/device validation with no driver complexity. The UFS stack provides a generic API set to access, control, and configure the bus driver, host controller driver, and the underlying hardware. The stack includes functions for UFS initialization, UniPro attributes configuration, sending/Receiving of commands/tasks in the form of UPIUs, data transfer, UFS interrupt handling, UFS device configuration, and UFS host controller hardware configuration. The UFS 2.1 Host Stack can support a single UFS host controller with a single UFS Device.</p>\r\n
\r\n <p>The UFS host stack consists of the following layers:</p>\r\n
\r\n <ul>\r\n
\t <li>a) Application Interface Layer (API Layer)</li>\r\n \t <li>b) Protocol Layer</li>\r\n \t <li>c) Host Controller Driver Layer</li>\r\n \t <li>d) Low level Hardware Abstraction Layer</li>\r\n \t <li>e) OS Abstraction Layer</li>\r\n </ul>\r\n
\r\n <p>The layered architecture allows for easy porting to various operating systems and various platforms. Client applications such as the function drivers interface with the API layer to use the UFS device. The low level details of the protocol is abstracted for the end-user and is handled in the software stack. A set of well defined APIs are provided at this layer.</p>
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\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>
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The UFS 2.1 Host Stack is a stack developed for Controllers that are used to connect devices via UniPro/M-PHY. can also be validating device during its development and integration life cycles thereby helping designers reduce the time market their product.\r\n
\r\n The modular architected OS platform independent which eases porting effort. It has thin hardware abstraction layers making it highly portable.\r\n
\r\n The low-level layer purely users use this alone host/device validation with no driver complexity. provides generic API set access control configure bus host controller underlying hardware. includes functions initialization UniPro attributes configuration sending/Receiving of commands/tasks in form UPIUs data transfer interrupt handling configuration. support single Device.\r\n
\r\n The consists following layers:\r\n
\r\n \r\n \t a) Application Interface Layer (API Layer)\r\n \t b) Protocol Layer\r\n \t c) Controller Driver Layer\r\n \t d) Low level Hardware Abstraction Layer\r\n \t e) Layer\r\n \r\n \r\n The layered architecture allows easy various operating systems platforms. Client applications such as function drivers interface device. low details protocol abstracted end-user handled software stack. A well defined APIs provided at layer. \r\n
\t Compliant JEDEC HCI 2.0 MIPI Specification version 1.6\r\n \t Portability choice processors hardware\r\n \t Easy-to-use applications\r\n \t Fully documented operation API\r\n \r\n \r\n
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<ul>\r\n
\t <li>Compliant with the following specifications\r\n \t <ul>\r\n \t\t <li>ESD220B UFS 2.0 compliant</li>\r\n \t\t <li>MIPI UniPro version 1.6</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Interface supported\r\n \t <ul>\r\n \t\t <li>AXI</li>\r\n \t\t <li>Optional AHB, OCP</li>\r\n \t\t <li>High-performance M-PHY v3.0 type 1</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Core features\r\n \t <ul>\r\n \t\t <li>2 lanes @ 5.9 Gbps per lane</li>\r\n \t\t <li>Low power with multiple power operating modes</li>\r\n \t\t <li>Configurable Transmit and Receive FIFOs</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Error detection and reporting. Support Data and Task management</li>\r\n \t <li>Support for multiple commands and tasks</li>\r\n </ul>
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<p>The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.</p>\r\n
\r\n <p>UFS 2.1 introduces new extensions to UFS 2.0</p>\r\n
\r\n <ul>\r\n
\t <li>Support for multiple initiators for a UFS target device</li>\r\n \t <li>Support for CMD priority for UPIUs</li>\r\n \t <li>Support for FFU (Field Firmware Update) using Write buffer SCSI CMD</li>\r\n \t <li>Support for data count (update in UPIU field) in terms of block size</li>\r\n </ul>\r\n
\r\n <p>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.</p>
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\t <li>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.</li>\r\n \t <li>The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.</li>\r\n </ul>
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The Universal Flash Storage (UFS) is a JEDEC data transfer standard designed for mobile systems. Most UFS applications require large storage capacity and boot code. Applications include phones tablets laptop PCs DSC PMP MP3 other requiring mass XiP or external cards. simple but high-performance serial interface that efficiently moves between host processor devices. transfers follow the SCSI model with subset of commands.\r\n
\r\n UFS 2.1 introduces new extensions to 2.0\r\n
\r\n \r\n \t Support multiple initiators target device\r\n \t Support CMD priority UPIUs\r\n \t Support FFU (Field Firmware Update) using Write buffer CMD\r\n \t Support count (update in UPIU field) terms block size\r\n \r\n \r\n The Device controller uses an M-PHY® 3.1 Adapter Layer backed by UniPro v1.6 Link layer as per specification. compliant IP cores are building blocks simplify interconnect architectures platforms. This leads smaller footprint greater interoperability chips devices from diverse sources lower power EMI. \r\n
\t Compliant following specifications\r\n \t \r\n \t\t ESD220B 2.0 compliant\r\n \t\t MIPI version 1.6\r\n \t \r\n \t \r\n \t Interface supported\r\n \t \r\n \t\t AXI\r\n \t\t Optional AHB OCP\r\n \t\t High-performance M-PHY v3.0 type 1\r\n \t \r\n \t \r\n \t Core features\r\n \t \r\n \t\t 2 lanes @ 5.9 Gbps lane\r\n \t\t Low operating modes\r\n \t\t Configurable Transmit Receive FIFOs\r\n \t \r\n \t \r\n \t Error detection reporting. Support Data Task management\r\n \t Support commands tasks\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n \t <li>High-speed mode Gear 1, Gear 2, Gear 3, and Gear 4.</li>\r\n \t <li>Supports 2 lanes for 23.3 Gbps max bandwidth</li>\r\n \t <li>Task management operations</li>\r\n \t <li>Supports multiple partitions (LUNs) (to dummy memory) with partition management</li>\r\n \t <li>Definable write-protect group size</li>\r\n \t <li>Boot mode operation</li>\r\n \t <li>Device enumeration and discovery</li>\r\n \t <li>Background operations</li>\r\n \t <li>Secure Erase and Trim operations enhance security</li>\r\n \t <li>Supports Write-protect option</li>\r\n </ul>
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<p>The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.</p>\r\n
\r\n <p>Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage and bootable storage memory with an option for an external card.</p>\r\n
\r\n <p>The IP incorporates the latest UFS Host Controller Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 IP is available in GDSII format for a variety of process technologies and MIPI UniProSM version 1.8 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation.</p>
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\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n </ul>
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The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance serial interface primarily used in mobile systems between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.\r\n
\r\n Mobile phones UMPC DSC PMP are some of the typical applications for UFS Host Controller IP. Majority these require bootable with an option external card.\r\n
\r\n The IP incorporates latest Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 available GDSII format variety process technologies UniProSM 1.8 link layer support multi-lane operation optional Unified Memory Architecture (UMA) implementation. \r\n
\t UFS Device configurations available\r\n \t Complete hardware implementation\r\n \t Interop-proven UniPro layer\r\n \t MIPI M-PHY 4.0 Interface\r\n \t High-speed mode Gear 1 2 3 4.\r\n \t Supports lanes 23.3 Gbps max bandwidth\r\n \t Task management operations\r\n \t Supports multiple partitions (LUNs) (to dummy memory) partition management\r\n \t Definable write-protect group size\r\n \t Boot operation\r\n \t Device enumeration discovery\r\n \t Background operations\r\n \t Secure Erase Trim operations enhance security\r\n \t Supports Write-protect option\r\n text_medium_priority " => ""
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\t <li>Compliant to MIPI Alliance Standard for M-PHY specification Version 3.1</li>\r\n \t <li>Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps</li>\r\n \t <li>Supports M-PHY Type-I system</li>\r\n \t <li>Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz</li>\r\n \t <li>Support for Clock and Data Recovery Options</li>\r\n \t <li>Supports low speed transfer G0-G7 with a bit rate of up to 576 Mbps</li>\r\n \t <li>PWM signalling for Low speed [LS] data</li>\r\n \t <li>Supports error detection mechanism for sequence errors and contentions</li>\r\n \t <li>Data lanes support transfer of data in high speed mode</li>\r\n \t <li>Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states</li>\r\n \t <li>Supports squelch detection</li>\r\n \t <li>Has clock divider unit to generate clock for parallel data reception and transmission from and to the PIF (RMMI)</li>\r\n \t <li>Activates and disconnects high speed terminators for reception and transmission</li>\r\n \t <li>Supports standard PHY transceiver compliant to MIPI Specification</li>\r\n \t <li>Supports standard PIF (RMMI) interface compliant to MIPI Specification.</li>\r\n \t <li>On-chip clock generation configurable for either transmitter or a receiver</li>\r\n \t <li>Testability for Tx, Rx and PLL</li>\r\n </ul>
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<p>MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.</p>\r\n
\r\n <p>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</p>\r\n
\r\n <p> </p>\r\n
\r\n <p>Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.</p>
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\t <li>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.</li>\r\n \t <li>The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.</li>\r\n \t <li>The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</li>\r\n </ul>
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MIPI M-PHY Specification Version 3.1 is a low pin count power efficient inter-chip serial interface with high bandwidth capabilities. A configuration (LINK) consists of minimum two unidirectional lanes along associated lane management logic. Each the module (M-TX) that communicates to corresponding (M-RX) on other chip via interconnect differential lines. The lines can carry both High-Speed (HS) and Low-Speed (LS) signals.\r\n
\r\n The M-PHYs are Type 1 which apply UFS LLI CSI-3 protocols. Multi-gear 3.0 analog transceivers speed PLL data recovery units as well state-machine control — all in single GDSII. link protocol-specific controller (host or device) compliant RMMI specification allows seamless integration IPs namely PHY into design.\r\n
\r\n \r\n
\r\n Arasan follows rigorous practice co-verifying controllers their PHY’s ensure they operate together intended. These Arasan’s software stacks mapped onto Hardware Validation Platforms used for early compatibility interoperability testing host/device platforms from Arasan number contributor members. This minimizes end-to-end risk customers. \r\n
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"keyfeatures " => "<ul><li>Compliant with the JEDEC UFS v3.1</li><li>Backward compatibility JEDEC UFS v3.0 & v2.1</li><li>TAG overlap/LBA overlap/Valid UPIU check</li><li>Maximum DATA OUT = 64KB</li><li>Maximum DATA IN = 64KB</li><li>Maximum RTT number= 8</li><li>CMD Queue Depth = 32</li><li>HW Auto NOP IN Response</li><li>HW Auto Query Response</li><li>HW Auto Write Function</li><li>Support HPB v1.0 (Host-aware Performance Booster)</li><li>Support EHS (Extra Header Segment)</li></ul> "
"keyfeatures_cn " => "<ul><li>符合JEDEC UFS v3.1的规定\r </li><li>向后兼容JEDEC UFS v3.0 & v2.1\r </li><li>TAG重叠/LBA重叠/有效的UPIU检查\r </li><li>最大的数据输出=64KB\r </li><li>最大的数据输入=64KB\r </li><li>最大的RTT数=8\r </li><li>CMD队列深度=32\r </li><li>HW Auto NOP IN Response\r </li><li>HW自动查询响应\r </li><li>HW 自动写入功能\r </li><li>支持HPB v1.0（主机感知性能增强器）。\r </li><li>支持EHS（额外头段）</li></ul> "
"keywords " => "Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low power serial interface that efficiently moves data between a host processor and mass storage devices. When our UFS Controller IP is combined with in-house developed UniPro Controller IP and M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution.<br />\n
Verification :<br />\n
IP Functionally is verified in NC – Verilog simulation software using test bench written in Verilog HDL
"""
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通用闪存（UFS）控制器IP符合最新的JEDEC UFS v3.1规范。UFS是高性能、低功耗的串行接口，可以有效地在主机处理器和大容量存储设备之间移动数据。<br />\r\n
客户的产品设计师能够用UFS控制器IP与内部开发的UniPro控制器IP和M-PHY IP轻松地集成PHY和控制器，并通过UFS IP解决方案加快产品的上市时间.<br />\r\n
验证：使用Verilog HDL编写的测试台在NC-Verilog模拟软件中进行功能验证
"""
"partnumber " => "MIPI UFS v3.1 Host Controller IP "
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<li>Backward compatibility JEDEC UFS v3.0 & v2.1</li>\n
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"shortdescription " => "MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro "
"shortdescription_cn " => "MIPI UFS v3.1主机控制器IP，兼容M-PHY和Unipro "
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"text_high_priority " => "MIPI UFS v3.1 Host Controller IP Compatible with M-PHY and Unipro T2M GmbH "
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Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The standard a high performance low power serial interface that efficiently moves data between host processor and mass storage devices. When our combined in-house developed UniPro M-PHY designers can easily integrate PHY controller risk accelerate time-to market solution.\n
Verification :\n
IP Functionally verified in NC – Verilog simulation software using test bench written HDL Compliant v3.1Backward compatibility v3.0 & v2.1TAG overlap/LBA overlap/Valid UPIU checkMaximum DATA OUT = 64KBMaximum IN RTT number= 8CMD Queue Depth 32HW Auto NOP ResponseHW Query Write FunctionSupport HPB v1.0 (Host-aware Performance Booster)Support EHS (Extra Header Segment)
"""
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"keyfeatures_cn " => "<ul><li>所有UPIU处理\r </li><li>数据导入、数据输出、命令、响应、RTT、查询、任务管理和拒绝\r </li><li>由UFS主机完全控制UIC层\r </li><li>错误报告和处理\r </li><li>命令、查询和任务管理与命令和查询和任务管理中基于索引的处理之间的优先级仲裁\r </li><li>支持针对UFS主机的32个UTP传输请求描述符和8个UTP任务管理描述符\r </li><li>支持引导LUN、RPMB和著名的LUN\r </li><li>优先级LUN处理\r </li><li>安全功能</li></ul> "
"keywords " => "Universal Flash Storage 2.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 3.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via a UFS Host, using MIPI UniPro as Link and PHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Host works seamlessly with any UFS Device, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.<br />\n
Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
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UFS是一种高性能串行接口，用于移动系统中，帮助主机处理器与闪存和其他非易失性存储器等大容量存储设备进行通信。这种通信是通过UFS主机实现的，使用MIPI UniPro作为链路和PHY层的PHY。UFS主机控制器接口负责管理主机软件与UFS设备之间的通信，用于数据传输。它还执行接口管理和电源管理/控制过程。我们的UFS主机可以与任何UFS设备无缝协作，配合MIPI UniPro和MPHY使用。此外，我们还提供包括软件和验证平台在内的完整解决方案。可配置选项包括：<br />\r\n
C端口<br />\r\n
符合UFS规范v2.1并且向后兼容<br />\r\n
AXI支持
"""
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UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Host using MIPI UniPro as Link PHY for layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Device along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v2.1 backward compatible tAXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingPriority arbitration UPIUs index-based processing within Command Query UPIUsSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 2.1 UFS Host Device MIPI MPHY Unipro 3.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove "
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"keyfeatures " => "<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li><li>AXI support</li><li>All UPIU processing</li><li>Data-in, data-out, command, response, RTT, query, task management and reject</li><li>Complete control of UIC Layer by UFS Host</li><li>Error reporting and handling</li><li>Support for 32 UTP transfer request descriptors and 8 UTP task management descriptors for UFS host</li><li>Support for Boot LUN, RPMB, and well-known LUNs</li><li>Device: Up to 8 LUNs configurable; up to 8 command queues in each LUN; up to 8 tasks handling for task management</li><li>Priority LUN handling</li><li>Security features</li></ul> "
"keyfeatures_cn " => "<ul><li>符合UFSv3.1规范，并向后兼容UFS v3.0和v2.1规范\r </li><li>支持AXI\r </li><li>支持所有UPIU处理\r </li><li>数据导入、数据输出、命令、响应、RTT、查询、任务管理和拒绝\r </li><li>由UFS主机完全控制UIC层\r </li><li>错误报告和处理\r </li><li>支持针对UFS主机的32个UTP传输请求描述符和8个UTP任务管理描述符\r </li><li>支持引导LUN、RPMB和著名的LUN\r </li><li>设备：最多可配置8个LUN；每个LUN中最多可配置8个命令队列；针对任务管理的最多8个任务处理\r </li><li>优先级LUN处理\r </li><li>安全功能</li></ul> "
"keywords " => "Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 3.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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"overview " => """
UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via UFS Device, using MIPI UniPro as Link and MPHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Device works seamlessly with any UFS Host, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.<br />\n
Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
"overview_cn " => """
UFS是用于主机处理器和大容量存储设备移动系统的高性能串行接口，如闪存和其他非易失性存储设备之间的通信。这种通信是通过UFS设备实现的，使用MIPI UniPro作为Link和MPHY作为PHY层。这种通信是通过UFS设备实现的，使用MIPI UniPro作为链接，MPHY作为PHY层。UFS主机控制器接口负责管理数据传输所需的主机软件和UFS设备之间的通信。它还执行接口管理和电源管理/控制过程。我们的UFS设备可以与任何UFS主机以及MIPI UniPro和MPHY无缝工作。这个IP的交付件可选择<br />\r\n
• C端口<br />\r\n
• 应用程序接口-APB或AXI :
"""
"partnumber " => "MIPI UFS v3.1 Device Controller IP "
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"provider.name " => "T2M GmbH "
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"provider.priority " => 2001
"provider.slug " => "t2m-gmbh "
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"seofeatures " => """
<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li>\n
<li>AXI support</li>\n
<li>All UPIU processing</li>\n
<li>Data-in, data-out, command, response, RTT, query, task management and reject</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro "
"shortdescription_cn " => "MIPI UFS v3.1 设备控制器IP，兼容M-PHY和Unipro "
"slug " => "mipi-ufs-v3-1-device-controller-ip-compatible-with-m-phy-and-unipro "
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"text_high_priority " => "MIPI UFS v3.1 Device Controller IP Compatible with M-PHY and Unipro T2M GmbH "
"text_low_priority " => """
UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Device using MIPI UniPro as Link MPHY for PHY layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Host along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v3.1 backward compatible v3.0 & v2.1AXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsDevice: Up LUNs configurable; up queues each LUN; tasks handling managementPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 3.1 UFS Host Device MIPI MPHY Unipro 3.0 2.1 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove proven "
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"keyfeatures " => "<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li><li>Programmable 1, 2, or 4 data lanes</li><li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li><li>Support for end-to-end flow control</li><li>Support for all traffic classes</li><li>Support for preemption of high-priority frames</li><li>Support for up to 32 C-Ports</li><li>Round Robin arbitration across C-Ports</li><li>Group acknowledgement of up to 16 frames per traffic class</li><li>Support for frame retransmission</li><li>Configurable buffer spaces</li><li>CSD, CSV support</li><li>Support for UniPro test feature</li><li>TMPI support</li><li>Efficient power management</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro标准V1.6标准和MPHY标准3.x标准\r </li><li>可编程的1、2或4个数据通道\r </li><li>支持M-PHY HS数据速率HS-Gear-1、Gear-2、Gear-3、A/B模式和PWM数据速率PWM-G1到PWM-G7\r </li><li>支持端到端流量控制\r </li><li>支持所有流量类\r </li><li>支持高优先级帧的抢占\r </li><li>支持多达32个c端口\r </li><li>跨c端口的循环仲裁\r </li><li>每个流量类最多16帧的组确认\r </li><li>框架重传支架\r </li><li>可配置缓冲区空间\r </li><li>CSD、CSV支持\r </li><li>支持UniPro测试功能\r </li><li>TMPI支持\r </li><li>高效的电源管理</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
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"logo2 " => "t2m-v2-66bb477f994ef.webp "
"name " => "asic.node "
"overview " => """
UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobile device. UniPro allows device components to utilize MIPI PHY layer to communicate and exchange data with devices on the other side of MIPI lanes. UniPro supports a wide range of device applications like application processor, camera controller, display controllers, and storage controllers like UFS or memory (RAM) controllers.<br />\n
Our MIPI UniPro is designed to be PHY-agnostic, supporting a wide range of applications simultaneously in the application layer. Our MIPI UniPro along with other application solutions like CSI-3 or UFS and MPHY offers an comprehensive solution
"""
"overview_cn " => "UniPro是由MIPI联盟定义的一种分层协议，用于连接移动设备内的设备和组件。UniPro允许设备组件利用MIPI物理层与MIPI通道另一端的设备进行通信和数据交换。UniPro支持广泛的设备应用，如应用处理器、相机控制器、显示控制器和存储控制器（如UFS或内存（RAM）控制器）。我们的MIPI UniPro设计为不依赖于PHY，能够在应用层同时支持广泛的应用。我们的MIPI UniPro与其他应用解决方案（如CSI-3或UFS）和MPHY一起提供了一个全面的解决方案。 "
"partnumber " => "MIPI Unipro v1.6 Controller IP "
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"provider.name " => "T2M GmbH "
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<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li>\n
<li>Programmable 1, 2, or 4 data lanes</li>\n
<li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li>\n
<li>Support for end-to-end flow control</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.6 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-6-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.6 Controller IP Compatible with M-PHY and UFS T2M GmbH "
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UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within mobile device. allows device to utilize PHY layer communicate exchange data with on other side of lanes. supports wide range applications like application processor camera controller display controllers storage UFS or memory (RAM) controllers.\n
Our designed be PHY-agnostic supporting simultaneously in layer. Our along solutions CSI-3 MPHY offers an comprehensive solution Compliant Standard V1.6 standard 3.xProgrammable 1 2 4 lanesSupport M-PHY HS rates HS-Gear-1 Gear-2 Gear-3 both A/B modes PWM PWM-G1 PWM-G7Support end-to-end flow controlSupport all traffic classesSupport preemption high-priority framesSupport up 32 C-PortsRound Robin arbitration across C-PortsGroup acknowledgement 16 frames per classSupport frame retransmissionConfigurable buffer spacesCSD CSV supportSupport test featureTMPI supportEfficient power management
"""
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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"keyfeatures " => "<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61 </li><li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute </li><li>Support Asymmetric lanes and Gears </li><li>Support Data Lanes connected 2 lanes </li><li>Support Slow/ Slow-Auto/ Fast/ Fast-Auto mode </li><li>Support PWMG1-G4/HSG1-G4/Rate A/B </li><li>Support Skip symbol insertion </li><li>Support Scramble function </li><li>Support Quality of Service Monitoring (QoS) </li><li>Support PHY test mode & UniPro test feature </li><li>Support Cport0 and TC0 </li><li>Support HW auto LinkStartUp </li><li>Maximum R/W Performance up to 2170MB/s </li><li>UniPro IP Power-Off in Hibernate state</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro v1.8规范，并向后兼容MIPI UniPro v1.61\r </li><li>支持HS-Gear4 M-PHY IP v4.1和对属性的访问\r </li><li>支持不对称的车道和齿轮\r </li><li>支持数据通道，连接了2条通道\r </li><li>支持慢、慢自动、快、快自动模式\r </li><li>支持PWMG1-G4/HSG1-G4/Rate A/B\r </li><li>支持跳过符号插入\r </li><li>支持痉挛功能\r </li><li>支持服务质量监控（QoS）\r </li><li>支持PHY测试模式和UniPro测试功能\r </li><li>支持Cport0和TC0\r </li><li>支持硬件自动链接启动\r </li><li>最大收发性能最高可达2170MB/s\r </li><li>UniPro IP断电</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
"logo " => "t2m-v2-66bb477f994ef.webp "
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"name " => "asic.node "
"overview " => "This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a MIPI M-PHY link. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. When this MIPI UniPro Controller IP is combined with Universal Flash Storage (UFS) Controller IP and also our M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution. "
"overview_cn " => """
MIPI UniPro控制器IP符合最新的MIPI UniPro v1.8规范，提供了通过MIPI M-PHY链接控制UniPro链接的能力。MIPI UniPro是一种高性能、 chip-to-chip、用于移动应用的串行互连总线。<br />\r\n
客户的产品设计师能够吧MIPI UniPro控制器IP与通用闪存（UFS）控制器IP以及M-PHY IP轻松地集成PHY和控制器 IP，降低产品研发风险很低，加快产品上市时间.<br />\r\n
<br />\r\n
"""
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<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61</li>\n
<li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute</li>\n
<li>Support Asymmetric lanes and Gears</li>\n
<li>Support Data Lanes connected 2 lanes</li>\n
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"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.8 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.8 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-8-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.8 Controller IP Compatible with M-PHY and UFS T2M GmbH "
"text_low_priority " => "This MIPI UniPro Controller IP is compliant with the latest v1.8 specification provides capability to control link over a M-PHY link. high-performance chip-to-chip serial interconnect bus for mobile applications. When this combined Universal Flash Storage (UFS) and also our designers can easily integrate PHY controller low risk accelerate time-to market UFS solution. Compliant backward compatible v1.61 Support HS-Gear4 v4.1 access attribute Asymmetric lanes Gears Data Lanes connected 2 Slow/ Slow-Auto/ Fast/ Fast-Auto mode PWMG1-G4/HSG1-G4/Rate A/B Skip symbol insertion Scramble function Quality of Service Monitoring (QoS) test & feature Cport0 TC0 HW auto LinkStartUp Maximum R/W Performance up 2170MB/s Power-Off in Hibernate state "
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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<p>UFS VIP is a comprehensive VIP solution portfolio for SoC and IP designs incorporating the UFS Host Controller (UFSHCI), UFS 4.0, and UME standard, in conjunction with the MIPI Unipro and M-PHY standards.</p>\r\n
\r\n <ul>\r\n
\t <li>UFS host supported two ways:\r\n \t <ul>\r\n \t\t <li>UFSHC 4.0 driver model supports UME 1.0 and implements UFSHCI programming interface, including host adapter to various host bus interfaces, including AMBA AXI and AHB</li>\r\n \t\t <li>Generic host model emulates UFSHC host driver and UFSHCI-based controller</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>UFS device model emulates simple UFS device, including sparse logical block storage and processes over 20 SCSI</li>\r\n \t <li>Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5</li>\r\n \t <li>Supports UFS DME and CPort users</li>\r\n \t <li>CPort adapter interfaces to Avery or third party UniPro IP/VIP, enabling mix and match between UFS and Unipro layers to support module-level integration and verification</li>\r\n \t <li>M-PHY model</li>\r\n \t <li>Support draft M-PHY 5.0 Multiple LANE provisions</li>\r\n \t <li>Multiple transmission modes include LS-MODE NRZ and PWM signaling Multiple power saving modes</li>\r\n \t <li>Support error injections (encoding, disparity, etc.)</li>\r\n \t <li>UniPro model\r\n \t <ul>\r\n \t\t <li>Emulates UniPro draft 2.0 protocol stack layers and M-PHY</li>\r\n \t\t <li>Supports all service primitives (SAP) and service data units (x_SDU)</li>\r\n \t\t <li>DME user supports all sequences of control, configuration, and status primitives</li>\r\n \t\t <li>Transport service</li>\r\n \t\t <li>Allocates connections between CPorts</li>\r\n \t\t <li>Schedules message transfers between CPort users</li>\r\n \t\t <li>Supports CPort signal interface</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Supports UniPro test feature</li>\r\n \t <li>Inject errors at all layers through callbacks</li>\r\n \t <li>Comprehensive assertions track UFS and MIPI compliance coverage</li>\r\n \t <li>Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences</li>\r\n \t <li>Tracker log monitors all levels and improves debug</li>\r\n \t <li>Comprehensive directed and constrained random compliance test suite for UFSHCI and UFS device achieves high protocol coverage</li>\r\n </ul>
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<p><strong>Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PHY</strong></p>\r\n
\r\n <p>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</p>\r\n
\r\n <p>With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work more on verifying both low-level and system-level functions.</p>\r\n
\r\n <p>Avery compliance test suites offer effective core-through-chip-level tests, includ ing those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.</p>
"""
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\t <li>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</li>\r\n </ul>
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Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS UniPro M-PHY\r\n
\r\n Avery UFS/Unipro VIP provides a comprehensive solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation robust packet physical layer controls error injection protocol checks coverage functional analyzer-like features for debugging performance analysis metrics.\r\n
\r\n With the capabilities Avery engineers can work more efficiently develop complex tests on verifying both low-level system-level functions.\r\n
\r\n Avery compliance test suites offer effective core-through-chip-level includ ing those used workshops well extended developed by to cover specification features. is portfolio SoC IP incorporating Host Controller (UFSHCI) 4.0 UME standard conjunction MIPI M-PHY standards.\r\n
\r\n \r\n \t UFS host supported two ways:\r\n \t \r\n \t\t UFSHC driver model supports 1.0 implements UFSHCI programming interface including adapter various bus AMBA AXI AHB\r\n \t\t Generic emulates UFSHC UFSHCI-based controller\r\n \t \r\n \t \r\n \t UFS device simple sparse logical block processes over 20 SCSI\r\n \t Supports command sets: Native SPC-4 SBC-3 SAM-5\r\n \t Supports DME CPort users\r\n \t CPort or third party IP/VIP enabling mix match between layers support module-level integration verification\r\n \t M-PHY model\r\n \t Support draft 5.0 Multiple LANE provisions\r\n \t Multiple transmission modes include LS-MODE NRZ PWM signaling power saving modes\r\n \t Support injections (encoding disparity etc.)\r\n \t UniPro model\r\n \t \r\n \t\t Emulates 2.0 stack M-PHY\r\n \t\t Supports all service primitives (SAP) data units (x_SDU)\r\n \t\t DME user sequences control configuration and status primitives\r\n \t\t Transport service\r\n \t\t Allocates connections CPorts\r\n \t\t Schedules message transfers users\r\n \t\t Supports signal interface\r\n \t \r\n \t \r\n \t Supports feature\r\n \t Inject errors at through callbacks\r\n \t Comprehensive assertions track coverage\r\n \t Functional tracks range FSMs operational sequences\r\n \t Tracker log monitors levels improves debug\r\n \t Comprehensive directed suite achieves high coverage\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>\r\n
\r\n <p> </p>
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<p>The UFS 2.1 Host Stack is a stack developed for UFS Host Controllers that are used to connect to UFS devices via UniPro/M-PHY. The stack can also be used for validating a UFS device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.</p>\r\n
\r\n <p>The modular UFS 2.1 Host Stack is architected to be OS and platform independent which eases porting effort. It has thin OS and hardware abstraction layers making it highly portable.</p>\r\n
\r\n <p>The UFS 2.1 Host Stack has a low-level hardware layer that is purely OS independent and users can use this layer alone for UFS host/device validation with no driver complexity. The UFS stack provides a generic API set to access, control, and configure the bus driver, host controller driver, and the underlying hardware. The stack includes functions for UFS initialization, UniPro attributes configuration, sending/Receiving of commands/tasks in the form of UPIUs, data transfer, UFS interrupt handling, UFS device configuration, and UFS host controller hardware configuration. The UFS 2.1 Host Stack can support a single UFS host controller with a single UFS Device.</p>\r\n
\r\n <p>The UFS host stack consists of the following layers:</p>\r\n
\r\n <ul>\r\n
\t <li>a) Application Interface Layer (API Layer)</li>\r\n \t <li>b) Protocol Layer</li>\r\n \t <li>c) Host Controller Driver Layer</li>\r\n \t <li>d) Low level Hardware Abstraction Layer</li>\r\n \t <li>e) OS Abstraction Layer</li>\r\n </ul>\r\n
\r\n <p>The layered architecture allows for easy porting to various operating systems and various platforms. Client applications such as the function drivers interface with the API layer to use the UFS device. The low level details of the protocol is abstracted for the end-user and is handled in the software stack. A set of well defined APIs are provided at this layer.</p>
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\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>
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The UFS 2.1 Host Stack is a stack developed for Controllers that are used to connect devices via UniPro/M-PHY. can also be validating device during its development and integration life cycles thereby helping designers reduce the time market their product.\r\n
\r\n The modular architected OS platform independent which eases porting effort. It has thin hardware abstraction layers making it highly portable.\r\n
\r\n The low-level layer purely users use this alone host/device validation with no driver complexity. provides generic API set access control configure bus host controller underlying hardware. includes functions initialization UniPro attributes configuration sending/Receiving of commands/tasks in form UPIUs data transfer interrupt handling configuration. support single Device.\r\n
\r\n The consists following layers:\r\n
\r\n \r\n \t a) Application Interface Layer (API Layer)\r\n \t b) Protocol Layer\r\n \t c) Controller Driver Layer\r\n \t d) Low level Hardware Abstraction Layer\r\n \t e) Layer\r\n \r\n \r\n The layered architecture allows easy various operating systems platforms. Client applications such as function drivers interface device. low details protocol abstracted end-user handled software stack. A well defined APIs provided at layer. \r\n
\t Compliant JEDEC HCI 2.0 MIPI Specification version 1.6\r\n \t Portability choice processors hardware\r\n \t Easy-to-use applications\r\n \t Fully documented operation API\r\n \r\n \r\n
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<ul>\r\n
\t <li>Compliant with the following specifications\r\n \t <ul>\r\n \t\t <li>ESD220B UFS 2.0 compliant</li>\r\n \t\t <li>MIPI UniPro version 1.6</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Interface supported\r\n \t <ul>\r\n \t\t <li>AXI</li>\r\n \t\t <li>Optional AHB, OCP</li>\r\n \t\t <li>High-performance M-PHY v3.0 type 1</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Core features\r\n \t <ul>\r\n \t\t <li>2 lanes @ 5.9 Gbps per lane</li>\r\n \t\t <li>Low power with multiple power operating modes</li>\r\n \t\t <li>Configurable Transmit and Receive FIFOs</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Error detection and reporting. Support Data and Task management</li>\r\n \t <li>Support for multiple commands and tasks</li>\r\n </ul>
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<p>The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.</p>\r\n
\r\n <p>UFS 2.1 introduces new extensions to UFS 2.0</p>\r\n
\r\n <ul>\r\n
\t <li>Support for multiple initiators for a UFS target device</li>\r\n \t <li>Support for CMD priority for UPIUs</li>\r\n \t <li>Support for FFU (Field Firmware Update) using Write buffer SCSI CMD</li>\r\n \t <li>Support for data count (update in UPIU field) in terms of block size</li>\r\n </ul>\r\n
\r\n <p>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.</p>
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\t <li>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.</li>\r\n \t <li>The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.</li>\r\n </ul>
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The Universal Flash Storage (UFS) is a JEDEC data transfer standard designed for mobile systems. Most UFS applications require large storage capacity and boot code. Applications include phones tablets laptop PCs DSC PMP MP3 other requiring mass XiP or external cards. simple but high-performance serial interface that efficiently moves between host processor devices. transfers follow the SCSI model with subset of commands.\r\n
\r\n UFS 2.1 introduces new extensions to 2.0\r\n
\r\n \r\n \t Support multiple initiators target device\r\n \t Support CMD priority UPIUs\r\n \t Support FFU (Field Firmware Update) using Write buffer CMD\r\n \t Support count (update in UPIU field) terms block size\r\n \r\n \r\n The Device controller uses an M-PHY® 3.1 Adapter Layer backed by UniPro v1.6 Link layer as per specification. compliant IP cores are building blocks simplify interconnect architectures platforms. This leads smaller footprint greater interoperability chips devices from diverse sources lower power EMI. \r\n
\t Compliant following specifications\r\n \t \r\n \t\t ESD220B 2.0 compliant\r\n \t\t MIPI version 1.6\r\n \t \r\n \t \r\n \t Interface supported\r\n \t \r\n \t\t AXI\r\n \t\t Optional AHB OCP\r\n \t\t High-performance M-PHY v3.0 type 1\r\n \t \r\n \t \r\n \t Core features\r\n \t \r\n \t\t 2 lanes @ 5.9 Gbps lane\r\n \t\t Low operating modes\r\n \t\t Configurable Transmit Receive FIFOs\r\n \t \r\n \t \r\n \t Error detection reporting. Support Data Task management\r\n \t Support commands tasks\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n \t <li>High-speed mode Gear 1, Gear 2, Gear 3, and Gear 4.</li>\r\n \t <li>Supports 2 lanes for 23.3 Gbps max bandwidth</li>\r\n \t <li>Task management operations</li>\r\n \t <li>Supports multiple partitions (LUNs) (to dummy memory) with partition management</li>\r\n \t <li>Definable write-protect group size</li>\r\n \t <li>Boot mode operation</li>\r\n \t <li>Device enumeration and discovery</li>\r\n \t <li>Background operations</li>\r\n \t <li>Secure Erase and Trim operations enhance security</li>\r\n \t <li>Supports Write-protect option</li>\r\n </ul>
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<p>The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.</p>\r\n
\r\n <p>Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage and bootable storage memory with an option for an external card.</p>\r\n
\r\n <p>The IP incorporates the latest UFS Host Controller Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 IP is available in GDSII format for a variety of process technologies and MIPI UniProSM version 1.8 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation.</p>
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\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n </ul>
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The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance serial interface primarily used in mobile systems between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.\r\n
\r\n Mobile phones UMPC DSC PMP are some of the typical applications for UFS Host Controller IP. Majority these require bootable with an option external card.\r\n
\r\n The IP incorporates latest Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 available GDSII format variety process technologies UniProSM 1.8 link layer support multi-lane operation optional Unified Memory Architecture (UMA) implementation. \r\n
\t UFS Device configurations available\r\n \t Complete hardware implementation\r\n \t Interop-proven UniPro layer\r\n \t MIPI M-PHY 4.0 Interface\r\n \t High-speed mode Gear 1 2 3 4.\r\n \t Supports lanes 23.3 Gbps max bandwidth\r\n \t Task management operations\r\n \t Supports multiple partitions (LUNs) (to dummy memory) partition management\r\n \t Definable write-protect group size\r\n \t Boot operation\r\n \t Device enumeration discovery\r\n \t Background operations\r\n \t Secure Erase Trim operations enhance security\r\n \t Supports Write-protect option\r\n text_medium_priority " => ""
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\t <li>Compliant to MIPI Alliance Standard for M-PHY specification Version 3.1</li>\r\n \t <li>Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps</li>\r\n \t <li>Supports M-PHY Type-I system</li>\r\n \t <li>Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz</li>\r\n \t <li>Support for Clock and Data Recovery Options</li>\r\n \t <li>Supports low speed transfer G0-G7 with a bit rate of up to 576 Mbps</li>\r\n \t <li>PWM signalling for Low speed [LS] data</li>\r\n \t <li>Supports error detection mechanism for sequence errors and contentions</li>\r\n \t <li>Data lanes support transfer of data in high speed mode</li>\r\n \t <li>Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states</li>\r\n \t <li>Supports squelch detection</li>\r\n \t <li>Has clock divider unit to generate clock for parallel data reception and transmission from and to the PIF (RMMI)</li>\r\n \t <li>Activates and disconnects high speed terminators for reception and transmission</li>\r\n \t <li>Supports standard PHY transceiver compliant to MIPI Specification</li>\r\n \t <li>Supports standard PIF (RMMI) interface compliant to MIPI Specification.</li>\r\n \t <li>On-chip clock generation configurable for either transmitter or a receiver</li>\r\n \t <li>Testability for Tx, Rx and PLL</li>\r\n </ul>
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<p>MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.</p>\r\n
\r\n <p>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</p>\r\n
\r\n <p> </p>\r\n
\r\n <p>Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.</p>
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\t <li>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.</li>\r\n \t <li>The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.</li>\r\n \t <li>The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</li>\r\n </ul>
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MIPI M-PHY Specification Version 3.1 is a low pin count power efficient inter-chip serial interface with high bandwidth capabilities. A configuration (LINK) consists of minimum two unidirectional lanes along associated lane management logic. Each the module (M-TX) that communicates to corresponding (M-RX) on other chip via interconnect differential lines. The lines can carry both High-Speed (HS) and Low-Speed (LS) signals.\r\n
\r\n The M-PHYs are Type 1 which apply UFS LLI CSI-3 protocols. Multi-gear 3.0 analog transceivers speed PLL data recovery units as well state-machine control — all in single GDSII. link protocol-specific controller (host or device) compliant RMMI specification allows seamless integration IPs namely PHY into design.\r\n
\r\n \r\n
\r\n Arasan follows rigorous practice co-verifying controllers their PHY’s ensure they operate together intended. These Arasan’s software stacks mapped onto Hardware Validation Platforms used for early compatibility interoperability testing host/device platforms from Arasan number contributor members. This minimizes end-to-end risk customers. \r\n
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"keyfeatures " => "<ul><li>Compliant with the JEDEC UFS v3.1</li><li>Backward compatibility JEDEC UFS v3.0 & v2.1</li><li>TAG overlap/LBA overlap/Valid UPIU check</li><li>Maximum DATA OUT = 64KB</li><li>Maximum DATA IN = 64KB</li><li>Maximum RTT number= 8</li><li>CMD Queue Depth = 32</li><li>HW Auto NOP IN Response</li><li>HW Auto Query Response</li><li>HW Auto Write Function</li><li>Support HPB v1.0 (Host-aware Performance Booster)</li><li>Support EHS (Extra Header Segment)</li></ul> "
"keyfeatures_cn " => "<ul><li>符合JEDEC UFS v3.1的规定\r </li><li>向后兼容JEDEC UFS v3.0 & v2.1\r </li><li>TAG重叠/LBA重叠/有效的UPIU检查\r </li><li>最大的数据输出=64KB\r </li><li>最大的数据输入=64KB\r </li><li>最大的RTT数=8\r </li><li>CMD队列深度=32\r </li><li>HW Auto NOP IN Response\r </li><li>HW自动查询响应\r </li><li>HW 自动写入功能\r </li><li>支持HPB v1.0（主机感知性能增强器）。\r </li><li>支持EHS（额外头段）</li></ul> "
"keywords " => "Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low power serial interface that efficiently moves data between a host processor and mass storage devices. When our UFS Controller IP is combined with in-house developed UniPro Controller IP and M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution.<br />\n
Verification :<br />\n
IP Functionally is verified in NC – Verilog simulation software using test bench written in Verilog HDL
"""
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通用闪存（UFS）控制器IP符合最新的JEDEC UFS v3.1规范。UFS是高性能、低功耗的串行接口，可以有效地在主机处理器和大容量存储设备之间移动数据。<br />\r\n
客户的产品设计师能够用UFS控制器IP与内部开发的UniPro控制器IP和M-PHY IP轻松地集成PHY和控制器，并通过UFS IP解决方案加快产品的上市时间.<br />\r\n
验证：使用Verilog HDL编写的测试台在NC-Verilog模拟软件中进行功能验证
"""
"partnumber " => "MIPI UFS v3.1 Host Controller IP "
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<li>Backward compatibility JEDEC UFS v3.0 & v2.1</li>\n
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"shortdescription " => "MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro "
"shortdescription_cn " => "MIPI UFS v3.1主机控制器IP，兼容M-PHY和Unipro "
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"text_high_priority " => "MIPI UFS v3.1 Host Controller IP Compatible with M-PHY and Unipro T2M GmbH "
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Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The standard a high performance low power serial interface that efficiently moves data between host processor and mass storage devices. When our combined in-house developed UniPro M-PHY designers can easily integrate PHY controller risk accelerate time-to market solution.\n
Verification :\n
IP Functionally verified in NC – Verilog simulation software using test bench written HDL Compliant v3.1Backward compatibility v3.0 & v2.1TAG overlap/LBA overlap/Valid UPIU checkMaximum DATA OUT = 64KBMaximum IN RTT number= 8CMD Queue Depth 32HW Auto NOP ResponseHW Query Write FunctionSupport HPB v1.0 (Host-aware Performance Booster)Support EHS (Extra Header Segment)
"""
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"keyfeatures_cn " => "<ul><li>所有UPIU处理\r </li><li>数据导入、数据输出、命令、响应、RTT、查询、任务管理和拒绝\r </li><li>由UFS主机完全控制UIC层\r </li><li>错误报告和处理\r </li><li>命令、查询和任务管理与命令和查询和任务管理中基于索引的处理之间的优先级仲裁\r </li><li>支持针对UFS主机的32个UTP传输请求描述符和8个UTP任务管理描述符\r </li><li>支持引导LUN、RPMB和著名的LUN\r </li><li>优先级LUN处理\r </li><li>安全功能</li></ul> "
"keywords " => "Universal Flash Storage 2.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 3.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via a UFS Host, using MIPI UniPro as Link and PHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Host works seamlessly with any UFS Device, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.<br />\n
Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
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UFS是一种高性能串行接口，用于移动系统中，帮助主机处理器与闪存和其他非易失性存储器等大容量存储设备进行通信。这种通信是通过UFS主机实现的，使用MIPI UniPro作为链路和PHY层的PHY。UFS主机控制器接口负责管理主机软件与UFS设备之间的通信，用于数据传输。它还执行接口管理和电源管理/控制过程。我们的UFS主机可以与任何UFS设备无缝协作，配合MIPI UniPro和MPHY使用。此外，我们还提供包括软件和验证平台在内的完整解决方案。可配置选项包括：<br />\r\n
C端口<br />\r\n
符合UFS规范v2.1并且向后兼容<br />\r\n
AXI支持
"""
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UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Host using MIPI UniPro as Link PHY for layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Device along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v2.1 backward compatible tAXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingPriority arbitration UPIUs index-based processing within Command Query UPIUsSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 2.1 UFS Host Device MIPI MPHY Unipro 3.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove "
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"keyfeatures " => "<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li><li>AXI support</li><li>All UPIU processing</li><li>Data-in, data-out, command, response, RTT, query, task management and reject</li><li>Complete control of UIC Layer by UFS Host</li><li>Error reporting and handling</li><li>Support for 32 UTP transfer request descriptors and 8 UTP task management descriptors for UFS host</li><li>Support for Boot LUN, RPMB, and well-known LUNs</li><li>Device: Up to 8 LUNs configurable; up to 8 command queues in each LUN; up to 8 tasks handling for task management</li><li>Priority LUN handling</li><li>Security features</li></ul> "
"keyfeatures_cn " => "<ul><li>符合UFSv3.1规范，并向后兼容UFS v3.0和v2.1规范\r </li><li>支持AXI\r </li><li>支持所有UPIU处理\r </li><li>数据导入、数据输出、命令、响应、RTT、查询、任务管理和拒绝\r </li><li>由UFS主机完全控制UIC层\r </li><li>错误报告和处理\r </li><li>支持针对UFS主机的32个UTP传输请求描述符和8个UTP任务管理描述符\r </li><li>支持引导LUN、RPMB和著名的LUN\r </li><li>设备：最多可配置8个LUN；每个LUN中最多可配置8个命令队列；针对任务管理的最多8个任务处理\r </li><li>优先级LUN处理\r </li><li>安全功能</li></ul> "
"keywords " => "Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 3.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass storage, LUN Handling, UPIU Procesing, UFS RTL Code, RPMB, UIC Layer, prove "
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"overview " => """
UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via UFS Device, using MIPI UniPro as Link and MPHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Device works seamlessly with any UFS Host, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.<br />\n
Configurable Options :<br />\n
• C-port<br />\n
• Application Interface – APB or AXI
"""
"overview_cn " => """
UFS是用于主机处理器和大容量存储设备移动系统的高性能串行接口，如闪存和其他非易失性存储设备之间的通信。这种通信是通过UFS设备实现的，使用MIPI UniPro作为Link和MPHY作为PHY层。这种通信是通过UFS设备实现的，使用MIPI UniPro作为链接，MPHY作为PHY层。UFS主机控制器接口负责管理数据传输所需的主机软件和UFS设备之间的通信。它还执行接口管理和电源管理/控制过程。我们的UFS设备可以与任何UFS主机以及MIPI UniPro和MPHY无缝工作。这个IP的交付件可选择<br />\r\n
• C端口<br />\r\n
• 应用程序接口-APB或AXI :
"""
"partnumber " => "MIPI UFS v3.1 Device Controller IP "
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"provider.name " => "T2M GmbH "
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"provider.priority " => 2001
"provider.slug " => "t2m-gmbh "
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"seofeatures " => """
<ul><li>Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1</li>\n
<li>AXI support</li>\n
<li>All UPIU processing</li>\n
<li>Data-in, data-out, command, response, RTT, query, task management and reject</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro "
"shortdescription_cn " => "MIPI UFS v3.1 设备控制器IP，兼容M-PHY和Unipro "
"slug " => "mipi-ufs-v3-1-device-controller-ip-compatible-with-m-phy-and-unipro "
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"text_high_priority " => "MIPI UFS v3.1 Device Controller IP Compatible with M-PHY and Unipro T2M GmbH "
"text_low_priority " => """
UFS is a high performance serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash other non-volatile memories. This communication achieved via Device using MIPI UniPro as Link MPHY for PHY layers. The controller responsible managing software device needed data transfers. It also performs management power /control processes. Our works seamlessly with any Host along MPHY. Additionally we provide complete solution including validation platforms.\n
Configurable Options :\n
• C-port\n
• Application Interface – APB or AXI Compliant Specification v3.1 backward compatible v3.0 & v2.1AXI supportAll UPIU processingData-in data-out command response RTT query task rejectComplete control of UIC Layer by HostError reporting handlingSupport 32 UTP transfer request descriptors 8 hostSupport Boot LUN RPMB well-known LUNsDevice: Up LUNs configurable; up queues each LUN; tasks handling managementPriority handlingSecurity features
"""
"text_medium_priority " => "Universal Flash Storage 3.1 UFS Host Device MIPI MPHY Unipro 3.0 2.1 1.8 4.1 interface Mobile phones UMPC DSC PMP mass storage LUN Handling UPIU Procesing RTL Code RPMB UIC Layer prove proven "
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"keyfeatures " => "<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li><li>Programmable 1, 2, or 4 data lanes</li><li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li><li>Support for end-to-end flow control</li><li>Support for all traffic classes</li><li>Support for preemption of high-priority frames</li><li>Support for up to 32 C-Ports</li><li>Round Robin arbitration across C-Ports</li><li>Group acknowledgement of up to 16 frames per traffic class</li><li>Support for frame retransmission</li><li>Configurable buffer spaces</li><li>CSD, CSV support</li><li>Support for UniPro test feature</li><li>TMPI support</li><li>Efficient power management</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro标准V1.6标准和MPHY标准3.x标准\r </li><li>可编程的1、2或4个数据通道\r </li><li>支持M-PHY HS数据速率HS-Gear-1、Gear-2、Gear-3、A/B模式和PWM数据速率PWM-G1到PWM-G7\r </li><li>支持端到端流量控制\r </li><li>支持所有流量类\r </li><li>支持高优先级帧的抢占\r </li><li>支持多达32个c端口\r </li><li>跨c端口的循环仲裁\r </li><li>每个流量类最多16帧的组确认\r </li><li>框架重传支架\r </li><li>可配置缓冲区空间\r </li><li>CSD、CSV支持\r </li><li>支持UniPro测试功能\r </li><li>TMPI支持\r </li><li>高效的电源管理</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
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"logo2 " => "t2m-v2-66bb477f994ef.webp "
"name " => "asic.node "
"overview " => """
UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobile device. UniPro allows device components to utilize MIPI PHY layer to communicate and exchange data with devices on the other side of MIPI lanes. UniPro supports a wide range of device applications like application processor, camera controller, display controllers, and storage controllers like UFS or memory (RAM) controllers.<br />\n
Our MIPI UniPro is designed to be PHY-agnostic, supporting a wide range of applications simultaneously in the application layer. Our MIPI UniPro along with other application solutions like CSI-3 or UFS and MPHY offers an comprehensive solution
"""
"overview_cn " => "UniPro是由MIPI联盟定义的一种分层协议，用于连接移动设备内的设备和组件。UniPro允许设备组件利用MIPI物理层与MIPI通道另一端的设备进行通信和数据交换。UniPro支持广泛的设备应用，如应用处理器、相机控制器、显示控制器和存储控制器（如UFS或内存（RAM）控制器）。我们的MIPI UniPro设计为不依赖于PHY，能够在应用层同时支持广泛的应用。我们的MIPI UniPro与其他应用解决方案（如CSI-3或UFS）和MPHY一起提供了一个全面的解决方案。 "
"partnumber " => "MIPI Unipro v1.6 Controller IP "
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"provider.name " => "T2M GmbH "
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<ul><li>Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x</li>\n
<li>Programmable 1, 2, or 4 data lanes</li>\n
<li>Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7</li>\n
<li>Support for end-to-end flow control</li>\n
</ul>
"""
"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.6 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-6-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.6 Controller IP Compatible with M-PHY and UFS T2M GmbH "
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UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within mobile device. allows device to utilize PHY layer communicate exchange data with on other side of lanes. supports wide range applications like application processor camera controller display controllers storage UFS or memory (RAM) controllers.\n
Our designed be PHY-agnostic supporting simultaneously in layer. Our along solutions CSI-3 MPHY offers an comprehensive solution Compliant Standard V1.6 standard 3.xProgrammable 1 2 4 lanesSupport M-PHY HS rates HS-Gear-1 Gear-2 Gear-3 both A/B modes PWM PWM-G1 PWM-G7Support end-to-end flow controlSupport all traffic classesSupport preemption high-priority framesSupport up 32 C-PortsRound Robin arbitration across C-PortsGroup acknowledgement 16 frames per classSupport frame retransmissionConfigurable buffer spacesCSD CSV supportSupport test featureTMPI supportEfficient power management
"""
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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"keyfeatures " => "<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61 </li><li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute </li><li>Support Asymmetric lanes and Gears </li><li>Support Data Lanes connected 2 lanes </li><li>Support Slow/ Slow-Auto/ Fast/ Fast-Auto mode </li><li>Support PWMG1-G4/HSG1-G4/Rate A/B </li><li>Support Skip symbol insertion </li><li>Support Scramble function </li><li>Support Quality of Service Monitoring (QoS) </li><li>Support PHY test mode & UniPro test feature </li><li>Support Cport0 and TC0 </li><li>Support HW auto LinkStartUp </li><li>Maximum R/W Performance up to 2170MB/s </li><li>UniPro IP Power-Off in Hibernate state</li></ul> "
"keyfeatures_cn " => "<ul><li>符合MIPI UniPro v1.8规范，并向后兼容MIPI UniPro v1.61\r </li><li>支持HS-Gear4 M-PHY IP v4.1和对属性的访问\r </li><li>支持不对称的车道和齿轮\r </li><li>支持数据通道，连接了2条通道\r </li><li>支持慢、慢自动、快、快自动模式\r </li><li>支持PWMG1-G4/HSG1-G4/Rate A/B\r </li><li>支持跳过符号插入\r </li><li>支持痉挛功能\r </li><li>支持服务质量监控（QoS）\r </li><li>支持PHY测试模式和UniPro测试功能\r </li><li>支持Cport0和TC0\r </li><li>支持硬件自动链接启动\r </li><li>最大收发性能最高可达2170MB/s\r </li><li>UniPro IP断电</li></ul> "
"keywords " => "Unipro Controller, MIPI Uniprov1.8, MIPI Unipro v1.6, silicon proven unipro,Universal Flash Storage 3.1, UFS Host, UFS Device, MIPI MPHY, MIPI Unipro, UFS 2.1, UFS 3.0, UFS 2.1, Unipro 1.8, MPHY 4.1, Storage interface, Mobile phones, UMPC, DSC, PMP, mass "
"logo " => "t2m-v2-66bb477f994ef.webp "
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"name " => "asic.node "
"overview " => "This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a MIPI M-PHY link. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. When this MIPI UniPro Controller IP is combined with Universal Flash Storage (UFS) Controller IP and also our M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution. "
"overview_cn " => """
MIPI UniPro控制器IP符合最新的MIPI UniPro v1.8规范，提供了通过MIPI M-PHY链接控制UniPro链接的能力。MIPI UniPro是一种高性能、 chip-to-chip、用于移动应用的串行互连总线。<br />\r\n
客户的产品设计师能够吧MIPI UniPro控制器IP与通用闪存（UFS）控制器IP以及M-PHY IP轻松地集成PHY和控制器 IP，降低产品研发风险很低，加快产品上市时间.<br />\r\n
<br />\r\n
"""
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<ul><li>Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61</li>\n
<li>Support HS-Gear4 M-PHY IP v4.1 and access to attribute</li>\n
<li>Support Asymmetric lanes and Gears</li>\n
<li>Support Data Lanes connected 2 lanes</li>\n
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"seofeatures_cn " => ""
"shortdescription " => "MIPI Unipro v1.8 Controller IP, Compatible with M-PHY and UFS "
"shortdescription_cn " => "MIPI Unipro v1.8 控制器IP，兼容M-PHY和UFS "
"slug " => "mipi-unipro-v1-8-controller-ip-compatible-with-m-phy-and-ufs "
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"text_high_priority " => "MIPI Unipro v1.8 Controller IP Compatible with M-PHY and UFS T2M GmbH "
"text_low_priority " => "This MIPI UniPro Controller IP is compliant with the latest v1.8 specification provides capability to control link over a M-PHY link. high-performance chip-to-chip serial interconnect bus for mobile applications. When this combined Universal Flash Storage (UFS) and also our designers can easily integrate PHY controller low risk accelerate time-to market UFS solution. Compliant backward compatible v1.61 Support HS-Gear4 v4.1 access attribute Asymmetric lanes Gears Data Lanes connected 2 Slow/ Slow-Auto/ Fast/ Fast-Auto mode PWMG1-G4/HSG1-G4/Rate A/B Skip symbol insertion Scramble function Quality of Service Monitoring (QoS) test & feature Cport0 TC0 HW auto LinkStartUp Maximum R/W Performance up 2170MB/s Power-Off in Hibernate state "
"text_medium_priority " => "Unipro Controller MIPI Uniprov1.8 v1.6 silicon proven unipro Universal Flash Storage 3.1 UFS Host Device MPHY 2.1 3.0 1.8 4.1 interface Mobile phones UMPC DSC PMP mass "
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<p>UFS VIP is a comprehensive VIP solution portfolio for SoC and IP designs incorporating the UFS Host Controller (UFSHCI), UFS 4.0, and UME standard, in conjunction with the MIPI Unipro and M-PHY standards.</p>\r\n
\r\n <ul>\r\n
\t <li>UFS host supported two ways:\r\n \t <ul>\r\n \t\t <li>UFSHC 4.0 driver model supports UME 1.0 and implements UFSHCI programming interface, including host adapter to various host bus interfaces, including AMBA AXI and AHB</li>\r\n \t\t <li>Generic host model emulates UFSHC host driver and UFSHCI-based controller</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>UFS device model emulates simple UFS device, including sparse logical block storage and processes over 20 SCSI</li>\r\n \t <li>Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5</li>\r\n \t <li>Supports UFS DME and CPort users</li>\r\n \t <li>CPort adapter interfaces to Avery or third party UniPro IP/VIP, enabling mix and match between UFS and Unipro layers to support module-level integration and verification</li>\r\n \t <li>M-PHY model</li>\r\n \t <li>Support draft M-PHY 5.0 Multiple LANE provisions</li>\r\n \t <li>Multiple transmission modes include LS-MODE NRZ and PWM signaling Multiple power saving modes</li>\r\n \t <li>Support error injections (encoding, disparity, etc.)</li>\r\n \t <li>UniPro model\r\n \t <ul>\r\n \t\t <li>Emulates UniPro draft 2.0 protocol stack layers and M-PHY</li>\r\n \t\t <li>Supports all service primitives (SAP) and service data units (x_SDU)</li>\r\n \t\t <li>DME user supports all sequences of control, configuration, and status primitives</li>\r\n \t\t <li>Transport service</li>\r\n \t\t <li>Allocates connections between CPorts</li>\r\n \t\t <li>Schedules message transfers between CPort users</li>\r\n \t\t <li>Supports CPort signal interface</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Supports UniPro test feature</li>\r\n \t <li>Inject errors at all layers through callbacks</li>\r\n \t <li>Comprehensive assertions track UFS and MIPI compliance coverage</li>\r\n \t <li>Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences</li>\r\n \t <li>Tracker log monitors all levels and improves debug</li>\r\n \t <li>Comprehensive directed and constrained random compliance test suite for UFSHCI and UFS device achieves high protocol coverage</li>\r\n </ul>
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<p><strong>Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PHY</strong></p>\r\n
\r\n <p>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</p>\r\n
\r\n <p>With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work more on verifying both low-level and system-level functions.</p>\r\n
\r\n <p>Avery compliance test suites offer effective core-through-chip-level tests, includ ing those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.</p>
"""
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\t <li>Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.</li>\r\n </ul>
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Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS UniPro M-PHY\r\n
\r\n Avery UFS/Unipro VIP provides a comprehensive solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation robust packet physical layer controls error injection protocol checks coverage functional analyzer-like features for debugging performance analysis metrics.\r\n
\r\n With the capabilities Avery engineers can work more efficiently develop complex tests on verifying both low-level system-level functions.\r\n
\r\n Avery compliance test suites offer effective core-through-chip-level includ ing those used workshops well extended developed by to cover specification features. is portfolio SoC IP incorporating Host Controller (UFSHCI) 4.0 UME standard conjunction MIPI M-PHY standards.\r\n
\r\n \r\n \t UFS host supported two ways:\r\n \t \r\n \t\t UFSHC driver model supports 1.0 implements UFSHCI programming interface including adapter various bus AMBA AXI AHB\r\n \t\t Generic emulates UFSHC UFSHCI-based controller\r\n \t \r\n \t \r\n \t UFS device simple sparse logical block processes over 20 SCSI\r\n \t Supports command sets: Native SPC-4 SBC-3 SAM-5\r\n \t Supports DME CPort users\r\n \t CPort or third party IP/VIP enabling mix match between layers support module-level integration verification\r\n \t M-PHY model\r\n \t Support draft 5.0 Multiple LANE provisions\r\n \t Multiple transmission modes include LS-MODE NRZ PWM signaling power saving modes\r\n \t Support injections (encoding disparity etc.)\r\n \t UniPro model\r\n \t \r\n \t\t Emulates 2.0 stack M-PHY\r\n \t\t Supports all service primitives (SAP) data units (x_SDU)\r\n \t\t DME user sequences control configuration and status primitives\r\n \t\t Transport service\r\n \t\t Allocates connections CPorts\r\n \t\t Schedules message transfers users\r\n \t\t Supports signal interface\r\n \t \r\n \t \r\n \t Supports feature\r\n \t Inject errors at through callbacks\r\n \t Comprehensive assertions track coverage\r\n \t Functional tracks range FSMs operational sequences\r\n \t Tracker log monitors levels improves debug\r\n \t Comprehensive directed suite achieves high coverage\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>\r\n
\r\n <p> </p>
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<p>The UFS 2.1 Host Stack is a stack developed for UFS Host Controllers that are used to connect to UFS devices via UniPro/M-PHY. The stack can also be used for validating a UFS device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.</p>\r\n
\r\n <p>The modular UFS 2.1 Host Stack is architected to be OS and platform independent which eases porting effort. It has thin OS and hardware abstraction layers making it highly portable.</p>\r\n
\r\n <p>The UFS 2.1 Host Stack has a low-level hardware layer that is purely OS independent and users can use this layer alone for UFS host/device validation with no driver complexity. The UFS stack provides a generic API set to access, control, and configure the bus driver, host controller driver, and the underlying hardware. The stack includes functions for UFS initialization, UniPro attributes configuration, sending/Receiving of commands/tasks in the form of UPIUs, data transfer, UFS interrupt handling, UFS device configuration, and UFS host controller hardware configuration. The UFS 2.1 Host Stack can support a single UFS host controller with a single UFS Device.</p>\r\n
\r\n <p>The UFS host stack consists of the following layers:</p>\r\n
\r\n <ul>\r\n
\t <li>a) Application Interface Layer (API Layer)</li>\r\n \t <li>b) Protocol Layer</li>\r\n \t <li>c) Host Controller Driver Layer</li>\r\n \t <li>d) Low level Hardware Abstraction Layer</li>\r\n \t <li>e) OS Abstraction Layer</li>\r\n </ul>\r\n
\r\n <p>The layered architecture allows for easy porting to various operating systems and various platforms. Client applications such as the function drivers interface with the API layer to use the UFS device. The low level details of the protocol is abstracted for the end-user and is handled in the software stack. A set of well defined APIs are provided at this layer.</p>
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\t <li>Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6</li>\r\n \t <li>Portability in choice of OS, processors and hardware</li>\r\n \t <li>Easy-to-use interface for applications</li>\r\n \t <li>Fully documented generic device operation API</li>\r\n </ul>
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The UFS 2.1 Host Stack is a stack developed for Controllers that are used to connect devices via UniPro/M-PHY. can also be validating device during its development and integration life cycles thereby helping designers reduce the time market their product.\r\n
\r\n The modular architected OS platform independent which eases porting effort. It has thin hardware abstraction layers making it highly portable.\r\n
\r\n The low-level layer purely users use this alone host/device validation with no driver complexity. provides generic API set access control configure bus host controller underlying hardware. includes functions initialization UniPro attributes configuration sending/Receiving of commands/tasks in form UPIUs data transfer interrupt handling configuration. support single Device.\r\n
\r\n The consists following layers:\r\n
\r\n \r\n \t a) Application Interface Layer (API Layer)\r\n \t b) Protocol Layer\r\n \t c) Controller Driver Layer\r\n \t d) Low level Hardware Abstraction Layer\r\n \t e) Layer\r\n \r\n \r\n The layered architecture allows easy various operating systems platforms. Client applications such as function drivers interface device. low details protocol abstracted end-user handled software stack. A well defined APIs provided at layer. \r\n
\t Compliant JEDEC HCI 2.0 MIPI Specification version 1.6\r\n \t Portability choice processors hardware\r\n \t Easy-to-use applications\r\n \t Fully documented operation API\r\n \r\n \r\n
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<ul>\r\n
\t <li>Compliant with the following specifications\r\n \t <ul>\r\n \t\t <li>ESD220B UFS 2.0 compliant</li>\r\n \t\t <li>MIPI UniPro version 1.6</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Interface supported\r\n \t <ul>\r\n \t\t <li>AXI</li>\r\n \t\t <li>Optional AHB, OCP</li>\r\n \t\t <li>High-performance M-PHY v3.0 type 1</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Core features\r\n \t <ul>\r\n \t\t <li>2 lanes @ 5.9 Gbps per lane</li>\r\n \t\t <li>Low power with multiple power operating modes</li>\r\n \t\t <li>Configurable Transmit and Receive FIFOs</li>\r\n \t </ul>\r\n \t </li>\r\n \t <li>Error detection and reporting. Support Data and Task management</li>\r\n \t <li>Support for multiple commands and tasks</li>\r\n </ul>
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<p>The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.</p>\r\n
\r\n <p>UFS 2.1 introduces new extensions to UFS 2.0</p>\r\n
\r\n <ul>\r\n
\t <li>Support for multiple initiators for a UFS target device</li>\r\n \t <li>Support for CMD priority for UPIUs</li>\r\n \t <li>Support for FFU (Field Firmware Update) using Write buffer SCSI CMD</li>\r\n \t <li>Support for data count (update in UPIU field) in terms of block size</li>\r\n </ul>\r\n
\r\n <p>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.</p>
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\t <li>The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.</li>\r\n \t <li>The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.</li>\r\n </ul>
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The Universal Flash Storage (UFS) is a JEDEC data transfer standard designed for mobile systems. Most UFS applications require large storage capacity and boot code. Applications include phones tablets laptop PCs DSC PMP MP3 other requiring mass XiP or external cards. simple but high-performance serial interface that efficiently moves between host processor devices. transfers follow the SCSI model with subset of commands.\r\n
\r\n UFS 2.1 introduces new extensions to 2.0\r\n
\r\n \r\n \t Support multiple initiators target device\r\n \t Support CMD priority UPIUs\r\n \t Support FFU (Field Firmware Update) using Write buffer CMD\r\n \t Support count (update in UPIU field) terms block size\r\n \r\n \r\n The Device controller uses an M-PHY® 3.1 Adapter Layer backed by UniPro v1.6 Link layer as per specification. compliant IP cores are building blocks simplify interconnect architectures platforms. This leads smaller footprint greater interoperability chips devices from diverse sources lower power EMI. \r\n
\t Compliant following specifications\r\n \t \r\n \t\t ESD220B 2.0 compliant\r\n \t\t MIPI version 1.6\r\n \t \r\n \t \r\n \t Interface supported\r\n \t \r\n \t\t AXI\r\n \t\t Optional AHB OCP\r\n \t\t High-performance M-PHY v3.0 type 1\r\n \t \r\n \t \r\n \t Core features\r\n \t \r\n \t\t 2 lanes @ 5.9 Gbps lane\r\n \t\t Low operating modes\r\n \t\t Configurable Transmit Receive FIFOs\r\n \t \r\n \t \r\n \t Error detection reporting. Support Data Task management\r\n \t Support commands tasks\r\n text_medium_priority " => ""
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<ul>\r\n
\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n \t <li>High-speed mode Gear 1, Gear 2, Gear 3, and Gear 4.</li>\r\n \t <li>Supports 2 lanes for 23.3 Gbps max bandwidth</li>\r\n \t <li>Task management operations</li>\r\n \t <li>Supports multiple partitions (LUNs) (to dummy memory) with partition management</li>\r\n \t <li>Definable write-protect group size</li>\r\n \t <li>Boot mode operation</li>\r\n \t <li>Device enumeration and discovery</li>\r\n \t <li>Background operations</li>\r\n \t <li>Secure Erase and Trim operations enhance security</li>\r\n \t <li>Supports Write-protect option</li>\r\n </ul>
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<p>The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.</p>\r\n
\r\n <p>Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage and bootable storage memory with an option for an external card.</p>\r\n
\r\n <p>The IP incorporates the latest UFS Host Controller Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 IP is available in GDSII format for a variety of process technologies and MIPI UniProSM version 1.8 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation.</p>
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\t <li>UFS 3.0 Host and Device configurations available</li>\r\n \t <li>Complete UFS 3.0 hardware implementation</li>\r\n \t <li>Interop-proven UniPro 1.8 link layer</li>\r\n \t <li>MIPI M-PHY 4.0 Interface</li>\r\n </ul>
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The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance serial interface primarily used in mobile systems between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.\r\n
\r\n Mobile phones UMPC DSC PMP are some of the typical applications for UFS Host Controller IP. Majority these require bootable with an option external card.\r\n
\r\n The IP incorporates latest Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 available GDSII format variety process technologies UniProSM 1.8 link layer support multi-lane operation optional Unified Memory Architecture (UMA) implementation. \r\n
\t UFS Device configurations available\r\n \t Complete hardware implementation\r\n \t Interop-proven UniPro layer\r\n \t MIPI M-PHY 4.0 Interface\r\n \t High-speed mode Gear 1 2 3 4.\r\n \t Supports lanes 23.3 Gbps max bandwidth\r\n \t Task management operations\r\n \t Supports multiple partitions (LUNs) (to dummy memory) partition management\r\n \t Definable write-protect group size\r\n \t Boot operation\r\n \t Device enumeration discovery\r\n \t Background operations\r\n \t Secure Erase Trim operations enhance security\r\n \t Supports Write-protect option\r\n text_medium_priority " => ""
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\t <li>Compliant to MIPI Alliance Standard for M-PHY specification Version 3.1</li>\r\n \t <li>Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps</li>\r\n \t <li>Supports M-PHY Type-I system</li>\r\n \t <li>Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz</li>\r\n \t <li>Support for Clock and Data Recovery Options</li>\r\n \t <li>Supports low speed transfer G0-G7 with a bit rate of up to 576 Mbps</li>\r\n \t <li>PWM signalling for Low speed [LS] data</li>\r\n \t <li>Supports error detection mechanism for sequence errors and contentions</li>\r\n \t <li>Data lanes support transfer of data in high speed mode</li>\r\n \t <li>Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states</li>\r\n \t <li>Supports squelch detection</li>\r\n \t <li>Has clock divider unit to generate clock for parallel data reception and transmission from and to the PIF (RMMI)</li>\r\n \t <li>Activates and disconnects high speed terminators for reception and transmission</li>\r\n \t <li>Supports standard PHY transceiver compliant to MIPI Specification</li>\r\n \t <li>Supports standard PIF (RMMI) interface compliant to MIPI Specification.</li>\r\n \t <li>On-chip clock generation configurable for either transmitter or a receiver</li>\r\n \t <li>Testability for Tx, Rx and PLL</li>\r\n </ul>
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<p>MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.</p>\r\n
\r\n <p>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</p>\r\n
\r\n <p> </p>\r\n
\r\n <p>Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.</p>
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\t <li>The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.</li>\r\n \t <li>The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.</li>\r\n \t <li>The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.</li>\r\n </ul>
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MIPI M-PHY Specification Version 3.1 is a low pin count power efficient inter-chip serial interface with high bandwidth capabilities. A configuration (LINK) consists of minimum two unidirectional lanes along associated lane management logic. Each the module (M-TX) that communicates to corresponding (M-RX) on other chip via interconnect differential lines. The lines can carry both High-Speed (HS) and Low-Speed (LS) signals.\r\n
\r\n The M-PHYs are Type 1 which apply UFS LLI CSI-3 protocols. Multi-gear 3.0 analog transceivers speed PLL data recovery units as well state-machine control — all in single GDSII. link protocol-specific controller (host or device) compliant RMMI specification allows seamless integration IPs namely PHY into design.\r\n
\r\n \r\n
\r\n Arasan follows rigorous practice co-verifying controllers their PHY’s ensure they operate together intended. These Arasan’s software stacks mapped onto Hardware Validation Platforms used for early compatibility interoperability testing host/device platforms from Arasan number contributor members. This minimizes end-to-end risk customers. \r\n
\t Compliant Alliance Standard 3.1\r\n \t Supports transfer G1A/B G2A/B G3A/B rates up 5830.4 Mbps\r\n \t Supports Type-I system\r\n \t Support reference clock frequencies 19.2MHz/26MHz/38.4MHz/52MHz\r\n \t Support Clock Data Recovery Options\r\n \t Supports G0-G7 bit rate 576 Mbps\r\n \t PWM signalling Low [LS] data\r\n \t Supports error detection mechanism sequence errors contentions\r\n \t Data support mode\r\n \t Supports LS burst HS STALL SLEEP HIBERN8 states\r\n \t Supports squelch detection\r\n \t Has divider unit generate parallel reception transmission PIF (RMMI)\r\n \t Activates disconnects terminators transmission\r\n \t Supports standard transceiver Specification\r\n \t Supports (RMMI) Specification.\r\n \t On-chip generation configurable either transmitter receiver\r\n \t Testability Tx Rx PLL\r\n text_medium_priority " => ""
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Ufs mipi
IP
UFS MIPI
IP
Compare
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IP
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MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS
Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x
Programmable 1, 2, or 4 data lanes
Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7
Support for end-to-end flow control
Verification IP for UFS
Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.
UFS 2.1 Stack & Driver
Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6
Portability in choice of OS, processors and hardware
Easy-to-use interface for applications
Fully documented generic device operation API
UFS 2.1 Device Controller IP
The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.
The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.
UFS 3.0 Host
UFS 3.0 Host and Device configurations available
Complete UFS 3.0 hardware implementation
Interop-proven UniPro 1.8 link layer
MIPI M-PHY 4.0 Interface
MIPI M-PHY® 3.1 Analog Transceiver
The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
