MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro

Overview

UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and other non-volatile memories. This communication is achieved via UFS Device, using MIPI UniPro as Link and MPHY for PHY layers. The UFS host controller interface is responsible for managing communication between host software and UFS device, needed for data transfers. It also performs interface management and power management /control processes. Our UFS Device works seamlessly with any UFS Host, along with MIPI UniPro and MPHY. Additionally we provide a complete solution including software and validation platforms.
Configurable Options :
• C-port
• Application Interface – APB or AXI

Key Features

  • Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1
  • AXI support
  • All UPIU processing
  • Data-in, data-out, command, response, RTT, query, task management and reject
  • Complete control of UIC Layer by UFS Host
  • Error reporting and handling
  • Support for 32 UTP transfer request descriptors and 8 UTP task management descriptors for UFS host
  • Support for Boot LUN, RPMB, and well-known LUNs
  • Device: Up to 8 LUNs configurable; up to 8 command queues in each LUN; up to 8 tasks handling for task management
  • Priority LUN handling
  • Security features

Benefits

  • Highly modular design
  • Fully synchronous design
  • Configurable IP

Block Diagram

MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro Block Diagram

Applications

  • IOT
  • Automotive
  • Storage
  • Consumer
  • Embedded
  • Enterprise

Deliverables

  • Configurable RTL Code
  • HDL-based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance Monitors
  • Configurable synthesis shell
  • Documentation
  • Design guide
  • Verification guide
  • Synthesis guide

Technical Specifications

Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
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Semiconductor IP