IP Catalog > UCIe PHY

UCIe PHY IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (51)
Compare 51 IP from 11 vendors (1 - 10)
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • Low Power Dual PHY for UCIe low cost robust Chiplets
    • Support standard chiplet use for UCIe standard to 16G
    • Supports Chip Scale Packaging with 250V ESD option
    • Build in Security and Probe function for KGD
  • 16G UCIe Standard PHY for TSMC 7nm
    • 16Gbps per pin and supports 12/8/4Gbps subrates
    • High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
    • BIST features ensure Known Good Die (KGD)
    • Sideband for link management and robust training
  • 16G UCIe Standard PHY for TSMC 3nm
    • 16Gbps per pin and supports 12/8/4Gbps subrates
    • High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
  • 16G UCIe Advanced PHY for TSMC 3nm
    • 16Gbps per pin and supports 12/8/4Gbps subrates
    • High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
    • BIST features ensure Known Good Die (KGD)
    • Sideband for link management and robust training
  • IPTD2D-A PHY and Controller
    • Supports CoWoSTM, INFOTM and EMIBTM package technologies
    • Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption
  • UCIe-S PHY and Controller
    • Supports MCM, BGA packages and Chiplet2Chiplet interconnects on PCB
    • Available process nodes: 28, 22, 16, 12, 7, 6nm
    • X16 and X32 PHY with bump maps defined in UCIe 2.0 specifications
    • Industry leading power consumption
  • UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
  • UCIe-S PHY for Standard Package (x16) in TSMC N5A, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N5A, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
×
Semiconductor IP