Overview
The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications. One chiplet for a wide range of packaging and end applications. The PHY is protocol compliant with UCIe-S, UCIe-A and UCIe-3D. But uses unique bump map design and architecture.
The Universal PHY is patent pending, and more details can be provided under NDA.
Key Features
- Novel Redundancy for Hi-Rel,
- Support for 16&18-bit wide data,
- Support Synchronous Operation,
- Supports Advanced packaging,
- Support Control Data Signalling,
- Configurable no-clock option.
Benefits
Suitable for IOT, and HPC one PHY
Block Diagram
Applications
Broad range of Chiplets and any packaging.
Technical Specifications
Foundry, Node
TSMC 28nm HPC+, TSMC 22ULL, TSMC 12 FFC
Maturity
Taped out Jun 25
Availability
2025
