Transceiver IP

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Compare 960 IP from 114 vendors (1 - 10)
  • 802.15.4G RF Transceiver
    • The RF Transceiver (B130RF15P4G) is a dual band (sub-1GHz and 2.4GHz band) integrated transceiver specially designed for smart metering and IEEE 802.15.4g related applications.
    Block Diagram -- 802.15.4G RF Transceiver
  • Sub-1GHz (699MHz-960MHz) fully integrated transceiver
    • The B40NLL_NBIOT_TRX is a sub-1GHz (699MHz-960MHz) fully integrated transceiver specially designed for Narrow-band IOT applications.
    • The device is comprised of RF frontend, Frac-N frequency synthesizer, LO chains, and analog baseband blocks.
    • The receive path (RX) has high dynamic range and sensitivity.
    Block Diagram -- Sub-1GHz (699MHz-960MHz) fully integrated transceiver
  • 0.9V SLVS Transceiver in TSMC 22nm
    • This SLVS I/O Library, implemented in TSMC 22nm with an 11P7M_5X1Z UT-AlRDL metal stack, provides a 0.9V differential transceiver optimized for low-power, high-speed operation.
    • Supporting data rates up to 200 Mbps and compliant with JESD8-13 SLVS standards, the library features strong power supply rejection, integrated 100 on-die termination, and robust 2 kV HBM / 500 V CDM ESD protection.
    Block Diagram -- 0.9V SLVS Transceiver in TSMC 22nm
  • 1.2V SLVS Transceiver in UMC 110nm
    • This library delivers a compact and reliable 1.2V SLVS transceiver solution in UMC 110nm, optimized for high-speed, low-power applications.
    • Featuring robust supply and ground noise rejection, 2kV HBM ESD protection, and integrated on die termination, this library provides both transmit and receive paths compliant with JESD8-13 SLVS standards at up to 200 Mbps.
    Block Diagram -- 1.2V SLVS Transceiver in UMC 110nm
  • High Performance Transceiver
    • Our FD-TRx Series is a transceiver comprising both of our breakthrough flagship FDDAC and FDADC technologies in a single chip offering a full solution for bi-directional connectivity.
    • Its ultra-wide coherent modulation bandwidth and low energy consumption make it ideally suited for wide bandwidth applications such as mmWave-WiFi, mmWave5G and 6G, radar, or satellite.
  • Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
    • The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performance applications.
    • This tri-band system delivers exceptional wireless communication capabilities with support for Wi-Fi 6/6E/n/g/b/a, enabling seamless connectivity across a wide frequency spectrum (5.925–7.125 GHz).
    • With support for advanced 4096-QAM modulation, the IP is capable of ultra-high data throughput, making it an ideal solution for bandwidth-intensive applications requiring low latency, fast data rates, and robust connectivity.
  • MIPI M-PHY® 3.1 Analog Transceiver
    • The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
    • The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 3.1 Analog Transceiver
  • MIPI D-PHY Analog Transceiver IP Core
    • The MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY specification version 1.1.
    • It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols at speeds up to 1.5Gbps per lane.
    • It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver.
    Block Diagram -- MIPI D-PHY Analog Transceiver IP Core
  • MIPI M-PHY® 4.1 Analog Transceiver
    • The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 4.1 Analog Transceiver
  • LVDS Transceiver in TSMC 28nm
    • This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity.
    • Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C).
    Block Diagram -- LVDS Transceiver in TSMC 28nm
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