Sidense IP
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Vital signs healthcare sensor interface
- Two Channels of multi-lead electrocardiogram (ECG)
- Temperature sensor
- Differential capacitive sensor channel
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SD4.x UHSII
- Fully compliant with UHSII specification Ver. 4.x
- Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
- Supports data rates from 390Mbps to 1.56Gbps/ch
- RCLK frequency: 26 to 56MHz
- Built-in PLL and clock recovery
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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1.8V Capable GPIO on Samsung Foundry 4nm FinFET
- The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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SOQPSK-TG Demodulator IP Core
- Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation. SOQPSK-TG provides constant-envelope modulation with continuous phase.
- This minimizes spectral occupancy and improves resistance to interference and nonlinear amplification.
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Protocol controller IP for a CAN FD light responder node
- The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.
- It supports CAN FD light responder communication according to ISO 11898-1:2024.
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Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
- The XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, or on an FPGA.
- Safety Element out of Context (SEooC) according to ISO 26262-11:2018 Clause.Developed according to the automotive cybersecurity standard ISO 21434.
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Safety Enhanced GPNPU Processor IP
- A True SDV Solution
- Fully programmable – ideal for long product life cycles
- Scalable multicore solutions up to 864 TOPS
- Solutions for ADAS, IVI and ECU products
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SLM SHS IP
- The SLM SHS IP is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP.
- It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores.
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