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SAR ADC IP

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Compare 177 IP from 44 vendors (1 - 10)
  • 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
    • The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
    • It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.
    Block Diagram -- 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
  • Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018
    • The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
    • The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s) and power consumption down to 1.9 µW. The input voltage range is quasi-rail-to-rail guaranteeing more than + 1.7 V@ 1.8V power supply.
    • An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.
    Block Diagram -- Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018
  • SAR ADC
    • High Sampling Rate: Capable of sampling up to 640 million samples per second, making it suitable for ultra-high-speed applications
    • 12-bit Resolution: Delivers 12-bit digital output, providing superior precision and accuracy in signal quantization
    • SAR Architecture: Ensures high speed and low latency with excellent power efficiency
    • Ultra-Low Power Consumption: Optimized for minimal power usage, ideal for energy-sensitive applications
    Block Diagram -- SAR ADC
  • 10/12-bit SAR ADC
    • The SAR ADC IP is a small-size, low power analog to digital converter which leverages charge-redistribution successive approximation technology
    • It offers a reliable solution of analog-to-digital signal conversion for general application
    • Innosilicon SAR ADC IP consists of input MUX, ADC core, and digital logic
    Block Diagram -- 10/12-bit SAR ADC
  • 10-Bit SAR ADC 5MSPS
    •  Fully Differential Mode: -0.6V–0.6V
    •  Pseudo Differential Mode: 0V-1.2V
    •  1.8V Analog/1.0V Digital
    •  Resolution: 10-bit
    Block Diagram -- 10-Bit SAR ADC 5MSPS
  • 10bit 1Msps SAR ADC IP Core
    • 10-bit Parallel Output.
    • Conversion time/Sampling frequency = 1 us/ 1Msps
    • CLOCK REQUIREMENT: 2 MHz- 20 MHz
    Block Diagram -- 10bit 1Msps SAR ADC IP Core
  • 12-bit, 2MS/s SAR ADC IP for Microcontroller Business in TSMC 55nm
    • 12-bit SAR ADC @ 2MS/s conversion range, working up-to 4MS/s.
    • Integrated PGA selectable with multiplexer.
    • The ADC power scales linearly with clock speed. (DC to 2Msps)
    • Zero DC power
  • Low-power, high-speed 11-bit, 8 GSPS SAR ADC - TSMC 28nm HPC+
    • 11-bit Resolution
    • 8 GSPS Sampling Rate
    • 264 mW Power Consumption
  • 12-bit 1-channel up to 1 MSPS low power SAR ADC
    • Global Foundries Embedded EEPROM 55nm
    • INL ±3LSB
    • DNL ±1LSB
    • SINAD 65dB@1MSPS
    Block Diagram -- 12-bit 1-channel up to 1 MSPS low power SAR ADC
  • 12-bit 1-channel up to 1.25MSPS SAR ADC
    • TSMC eFlash 28nm technology
    • INL ±3LSB
    • DNL ±1LSB
    • SINAD 64dB@5V (1.25MSPS)
    Block Diagram -- 12-bit 1-channel up to 1.25MSPS SAR ADC
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