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Reed Solomon IP

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  • Reed Solomon II Intel® FPGA IP Core
    • The Reed Solomon II Intel® FPGA intellectual property (IP) core offers a fully parameterizable Reed Solomon encoder and decoder
    • These encoders and decoders are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data
    • The Reed Solomon II Intel FPGA IP core is designed to support optical transport network (OTN) applications.
  • High-Speed Reed Solomon Intel® FPGA IP Core
    • The High-Speed Reed Solomon Intel® FPGA intellectual property (IP) core uses a large parallel architecture to achieve a large throughput for applications that require 100 Gbps
    • The IP core is suitable for 10G (such as OTN) or 100G Ethernet (IEEE 802.3bj/bm) applications.
  • Reed Solomon FEC Codec
    • Reed Solomon IP core codec is based on IEEE 802.3bj Clause 91 specification.
    • The cyclic code used is RS (528,514) for 7 symbol error correction and RS (544,514) for 15 symbol error correction.
    • Encoder and Decoder are separate synthesizable cores. Different architectures are available to meet area and throughput requirements. 
  • Reed Solomon Decoder and Encoder FEC
    • High performance Reed Solomon IP Core (Encoder and Decoder)
    • Supports error and erasure decoding
    • Parameterized codeword length
  • Reed Solomon FEC
    • Designed to support any Reed Solomon code.
    • Custom tailored to support specific codes see standard table below
    • Low Latency
    • FEC Processing cycles optimized for reduced buffering
    Block Diagram -- Reed Solomon FEC
  • Reed Solomon Error Correcting Code ECC
    • Asynchronous operation
    • No clocks required.
    • No storage like memories SRAMS/ROMS/FilipFlops used
    • No iterative Feedback in the pipeline
    Block Diagram -- Reed Solomon Error Correcting Code ECC
  • Reed Solomon Erasure Code
    • Asynchronous operation
    • No clocks required.
    • No storage like memories SRAMS/ROMS/FilipFlops used
    • No iterative Feedback in the pipeline
    Block Diagram -- Reed Solomon Erasure Code
  • Reed Solomon Encoder
    • Parameterizable bits per symbol
    • Programmable codeword length
    • Programmable number of errors
    Block Diagram -- Reed Solomon Encoder
  • Reed Solomon Decoder
    • Parameterizable bits per symbol
    • Programmable codeword length
    • Programmable number of errors
    Block Diagram -- Reed Solomon Decoder
  • Reed Solomon
    • High-performance Reed Solomon IP Core (Encoder and Decoder)
    • Supports error and erasure decoding
    • Parameterized codeword length
    • Code generator polynomial: (x + ?0)(x + ?1)(x + ?2) . . . (x + ?15)
    Block Diagram -- Reed Solomon
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