Reed Solomon Error Correcting Code ECC

Overview

RS Code Statistics for different values of `$mm` `$tt`

Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Error correction FEC:

The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.

Symbol size is ‘m’ bits for all Galois Field operations.

Key Features

Asynchronous operation
No clocks required.
No storage like memories SRAMS/ROMS/FilipFlops used
No iterative Feedback in the pipeline
All operation is performed in 0 clock cycles.
RTL code is generated with parameters of

“m” the degree of primitive polynomial
“t_max” maximum value of error symbols that can be corrected.
corrects up to maximum number of erasure positions
number of symbols by which the code is shortened.
The number of error symbols (“t”) is programmable upto “t_max” .

Separate encoders are for every “t” .
Decoder shared for various values of “t” upto “t_max”
Lint clean code, verified for various values of “m”, “t_max”, “t” and shortened code.
Size of code differs for various values of “m”, “t_max” and number of symbols by which the code is shortened.

Block Diagram

Applications

SSD Controller
Space Communications
QR Code
Optical Communication
High Speed Communications
SRAMS in chips ASICS can have memory repair using this circuit
memory ECC in BIST

Hamming Code will protect against 1 bit errors and detect only upto 2 bit errors
RS Code can correct upto `$tt` symbol errors where `$tt` is decided when code is generated
RS Code can detect if more than `$tt` symbol errors have occurred.

Clause 91 8023bj-2014 [8023bs-2017 – 400g] RS(528,514) T=7 25Gb/s KR4 RS(544,530) T=15 100G KP4
802.3-2015 section 5 RS(144,128) RS(240,224) RS(255,239,8) RS(255,223) bb=32
802.3bs RS(576, 514, t=31, m=10)
PCI Express Gen 6

Technical Specifications

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