IP Catalog > RISC‑V

RISC‑V IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (229)
Compare 229 IP from 59 vendors (1 - 10)
  • Custom RISC-V Processor
    • Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
    • Keysom processors deliver powerful capabilities, optimizing IoT and AI workflows with energy-efficient, small-footprint solutions.
    Block Diagram -- Custom RISC-V Processor
  • RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
    • Built on RISC-V and delivered as soft chiplet IP, the Veyron E2X provides scalable, standards-based AI acceleration that customers can integrate and customize freely.
    Block Diagram -- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
  • RISC-V System IP
    • Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V simplifying system principles.
  • Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
    • 11+ SPECint2017 (rate=1) at up to 4.2 GHz
    • Enhanced RISC-V standard matrix extension support alongside RVV 1.0 and scalar compute
    • 24 TeraFLOPS/core of FP8 matrix compute for AI/ML acceleration, or up to 4.5 PFLOPS in a 192-core chiplet-based SiP
    • Significantly higher IPC and performance-per-watt, driven by new microarchitecture innovations
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
    • AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
    • It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
  • All-In-One RISC-V NPU
    • Optimized Neural Processing for Next-Generation Machine Learning with High-Efficiency and Scalable AI compute
    Block Diagram -- All-In-One RISC-V NPU
  • Configurable RISC-V processor IP core
    • The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
    • The architecture is designed to utilize a small area footprint and to maintain execution predictability.
    Block Diagram -- Configurable RISC-V processor IP core
  • MIPI I3C Master RISC-V based subsystem
    • RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors
    • All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface
    Block Diagram -- MIPI I3C Master RISC-V based subsystem
  • ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
    • The AndesCore™ D23-SE is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability.
    • In addition to commonly used RISC-V IMAC, single/double precision FPU and DSP extensions, it supports the recently ratified ISA extensions such as B (bit manipulation), K (scalar cryptography), CMO (cache management operations) as well as Zce (code size reduction), plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
×
Semiconductor IP