Risc‑v IP

Compare 199 IP from 50 vendors (1 - 10)

RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
Tessent RISC-V trace and debug
- Instruction trace
- Efficient packet format
- Fast profiling
- Multiple retirement
32 Bit - Embedded RISC-V Processor Core
- 32 bit,
- 3-stage pipeline,
- 32 registers
32 bit - Compact RISC-V Processor Core
- 32-bit RISC-V core
- RV32EMC instruction set
- 16 general purpose registers
RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2
TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
32 Bit - Embedded RISC-V Processor Core
- Best-in-class performance for small-area and low-power applications
- Highly configurable and easy and quick to customize and verify
- Process compliant with ISO 26262 and ISO 21434

RISC‑V IP