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PCIe Clock PHY IP

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Compare 315 IP from 20 vendors (1 - 10)
  • PCIe 4.0 PHY on 5nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 4.0 PHY on 5nm
  • PCIe 6.0 PHY on 5nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 6.0 PHY on 5nm
  • PCIe 4.0 PHY on 8nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 4.0 PHY on 8nm
  • PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
    • Compliant with PCIe 3.0 Base Specification
    • Compliant with PIPE 4.3
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
  • PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
    • Fully compliant with PCI Express Base 5.0 electrical specifications
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
    Block Diagram -- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
  • 25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
  • 25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation
  • 25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation
  • 25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation
  • 25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
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