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               Supports PCI specs mPCIe PIPE PCS/PMA Message Bus SERDES interface MPHY RMMI serial - > All error injections layer protocol checks for PWM HS gears as by MPCIe lane configurations Automatic clock recovery asymmetrical configuration dynamic bandwidth scalability per APIs supplied well C DPI exports Support Generations including SSC Configurable Linkwidths x1 x2 x4 x8 x12 x16 x32 Upconfiguration polarity inversion lane-to-lane skew Full link width negotiation 32 Lanes Lane Reversal ASPM Software controlled Power Management LTSSM state machine DL machines Automated Error Injections at all layers Checkers timing functional accuracy each Queuing 8 VCs configurable depth TC VC queue mapping multiple Requestor / Completer applications user User direct TLP queuing receipt Checks TLPs correct formation header payload prefix ECRC framing LCRC rules Check DLLP fields formatting Interface send receive defined DLLPs model Spread Spectrum Clocking (SSC) Gen 1 2 8b/10b encoding 3 4 5 128b/130b 6 1b/1b timers timeouts Callbacks Root complex End point monitor processing data. Notifies testbench significant events such transactions warnings violations complete testsuite test every feature specification scoreboard checking Built-in monitors a global bus instantiations create environment Functional coverage features Scaled Flow Control Margining Receiver VF 10-Bit Tag Requester Alternate Negotiation Conventional Advanced Features Gray coding Precoding Flit mode Non-flit Forward Correction mechanism Code L0p Shared Credit Pool Link management IDE Functionality DOE SR-IOV \n
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              PCI Express Transactor Synthesizable \n
               SmartDV Technologies
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              PCIE Synthesizable Transactor provides a smart way to verify the component of SOC or ASIC in Emulator FPGA platform. The SmartDV's is fully compliant with standard Specification and following features. \n
                Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0. MPCIE PIPE PCS/PMA serdes interface MPHY RMMI serial Interface all error injections layer protocol checks for PWM HS gears as supported by lane configurations automatic clock recovery mode asymmetrical configuration dynamic bandwidth scalability per both Rate A B UVM Verilog APIs supplied well C DPI exports Gen 1 2 3 4 5 6 including SSC full link speed width negotiation up 32 Lanes automated Error Injections at layers Checkers timing functional accuracy each queuing 8 VCs configurable depth Configurable TC VC queue mapping Multiple Requester / Completer applications user User direct TLP receipt Check TLPs correct formation headers prefixes ECRC DL state machines framing LCRC rules DLLP fields formatting send receive defined DLLPs ASPM Software controlled Power Management checking LTSSM machine model digital Link Width Up configure polarity inversion lane-to-lane skew Spread Spectrum Clocking (SSC) gen PCS 8b/10b encoding 128b/130b flit based encoding. timers timeouts scaled Flow Control data Feature Exchange Margining Receiver vF 10-Bit Tag enhanced Allocation emergency Reduction State synthesizable static synchronous design positive edge clocking no internal tri-states simple allows easy connection microprocessor/microcontroller devices Compliant 5.2.1
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M-pcie IP
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M-PCIe IP

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Compare 3 IP from 1 vendors (1 - 3)
  • MPCIE Verification IP
    • Supports PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • Supports MPHY RMMI and serial interface
    • - > All error injections in MPHY layer
    • - > All protocol checks for MPHY layer
    Block Diagram -- MPCIE Verification IP
  • PCI Express Verification IP
    • Supports PCI Express specs 1.0/2.0/2.1/3.0/4.0/5.0/6.0
    • Supports mPCIe
    • Supports PIPE, PCS/PMA, Message Bus and SERDES interface
    • Supports MPHY RMMI and serial interface
    Block Diagram -- PCI Express Verification IP
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
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