Low Power Memory Compiler IP
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Ultra-low-leakage even in a generic process
- No leakage in memory plane
- Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
- Key patent for high density with only one programming layer
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Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM at nominal voltage
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Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM at nominal voltage
-
Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM
-
Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM
-
VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
- Low Power
- High Density
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down