UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
Overview
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
Technical Specifications
Foundry, Node
UMC 40nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
40nm
,
40nm
LP
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