Interface IP
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NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
- This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.
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NFC wireless interface supporting ISO14443 A and B on SMIC 180nm
- The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
- This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.
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ION 64b66b IP (64b/66b High-speed Serial Interface)
- ION 64b66b is an IP for high-speed serial interface targeting applications with inter-chip and inter-board connections.
- Lightweight link layer protocol provides one-to-one data movement via one or more high-speed serial lanes.
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ION 8b10b IP (8b/10b High-speed Serial Interface)
- ION 8b10b is a high-speed serial interface targeting applications with inter-chip and inter-board connections.
- Lightweight link layer protocol provides one-to-one data movement via one or more high-speed serial lanes.
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Quad Serial Gigabit Media Independent Interface (QSGMII)
- QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps.
- It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
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Universal Serial 10GE Media Independent Interface (USXGMII)
- The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
- Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
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Serial Gigabit Media Independent Interface (SGMII)
- SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MAC (Media Access Controller) to a PHY (Physical Layer Device).
- It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
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RSA2-AHB Accelerator Core with AHB Interface
- The core implements the exponentiation operation of the RSA cryptography Q = Pk.
- The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
- Once the operation is complete, the result Q can be read through the AHB interface.
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USB 2.0 Human Interface Devices Design Platform
- The USB 2.0 HID Design Platform is a complete, integrated solution, dedicated to a wide range of USB-based Human Interface Devices, like mouse, keyboard, and tablet.
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Combination MIPI CPHY-DPHY Analog Interface
- The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
- It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
- The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires
