IEEE 1588 IP
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118
IP
from 26 vendors
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10)
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Gigabit Ethernet with IEEE 1588 and AVB
- The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol extensions for Audio Video Bridging (AVB).
- The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Media Independent Interface (GMII).
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IEEE 1588 IIP
- Compliant with IEEE Standard 1588-2019 specification
- Supports for TSN required PTP as per IEEE 802.1AS
- Configurable as PTP Master or PTP Slave
- Supports both end to end and peer to peer delay mechanism
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IEEE 1588 V2 Ordinary and Boundary Clock
- Hardware features:
- Software features:
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IEEE 1588 V2 CPU-less Slave Clock
- IP core netlist ready for seamless integration in ISE design flow
- Reference design for AVNET Spartan-6 FPGA LX9 Microboard
- Available profiles: Power, IEC 61850 and Telecom
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IEEE 1588 Boundary, Slave And Master Clock
- IEEE 1588 v2 compliant Boundary Clock and Master/Slave Ordinary Clock IP core
- ToD error is better than ±1µsec on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Frequency accuracy performance is better than 16ppb on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Standard compliant Best Master Clock (BMC) algorithm
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IEEE 1588 Boundary, Slave And Master Clock
- Standalone IEEE1588v2 standard compliant BC and Master/Slave OC chip on FPGA
- Hybrid 1588/SyncE mode support
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IEEE 1588 Boundary, Slave And Master Clock
- Standalone IEEE 1588 v2 standard compliant Boundary Clock (BC) and Ordinary Clock (OC) Master/Slave IP core for Xilinx Spartan-6
- Excellent synchronization performance over most extreme packet transport network conditions
- Slave meets 3G, 4G-LTE and 5G synchronization requirements
- Adaptive to network impairments
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syn1588® enabled IEEE 1588 compliant clock synchronisation
- fully synchronous to the system clock
- all registers of the core operate with the rising clock edge
- well commented, structured VHDL source code
- medium footprint and medium I/O count
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Verification IP for Ethernet
- Avery TSN Ethernet Verification IP provides a complete simulation-based func tional verification solution for core-level and SoC-level verification, including MAC and PHY models, protocol checking, and optional compliance test suite based on UNH-IOL test specifications.
- Additional integration with ARM® Fast Model integration enables running the TSN IP’s software stack in one fully integrated testbench.
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Triple-Speed Ethernet FPGA IP
- The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) Intellectual Property (IP).
- This IP function enables FPGAs to interface to an external Ethernet PHY device, which interfaces to the Ethernet network.
