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Search (265)
Compare 265 IP from 41 vendors (1 - 10)
  • VIRTUAL GPIO IIP
    • Compliant with standard protocol of MIPI Virtual GPIO v0.9 specification
    • Bi-directional Virtual GPIO state information exchange
    • Transmission latency within the permissible limits
    • Wide range of clock frequency support (from sleep clock to higher frequency (78 MHz)
    Block Diagram -- VIRTUAL GPIO IIP
  • GPIO IIP
    • Compliant with standard protocol of GPIO specification
    • Supports single channel
    • Supports configurable channel width for GPIO pins from 1 to 32 bits
    • Supports dynamic programming of each GPIO bit as input or output
    Block Diagram -- GPIO IIP
  • GPIO Verification IP
    • Available in native System Verilog (UVM/OVM/ VMM) and Verilog
    • Unique development methodology to ensure the highest levels of quality
    • Availability of Compliance & Regression Test Suites
    • 24X5 customer support
    Block Diagram -- GPIO Verification IP
  • 180nm I/O Library with 1.5V to 3.3V GPIO
    • Core Device: 1.6V
    • I/O Device: 6V
    • BEOL: 1P5M
    • Pad: Wire bond, 110um inline pitch
  • A 65nm/55nm Wirebond IO Library with 1.2V to 3.3V GPIO and 5V ODIO
    • A 3.3V GPIO with two selectable inputs, slew rate control, and optional active tri-state.
    • A GPIO with an ultra-wide supply range and an optional glitch filter
    • A 5V tolerant Open drain IO with an optional glitch filter and programmable receiver thresholds
    • A 1.2V Open drain IO with two slew rate options.
  • Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain in 110nm
    • Multi-voltage 1.8V / 3.3V Fail-Safe GPIO
    • 3.3V ODIO
    • GPIO: 100MHz at 75pF
    • 3.3V programming gate cell
  • Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain in 110nm
    • Multi-voltage 1.8V / 3.3V Fail-Safe GPIO
    • 3.3V ODIO
    • GPIO: 100MHz at 75pF
    • 3.3V programming gate cell
  • IO 1.8V GPIO in Samsung (4nm)
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
  • IO 1.2V GPIO in Samsung (4nm)
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
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Semiconductor IP