A Fail-Safe Digital I/O Library.
This silicon-proven TSMC 28nm Digital I/O Library delivers a high-performance, low-power interface solution designed for advanced digital applications. Featuring a triple-staggered architecture, this versatile library supports multi-voltage and multi-protocol GPIO, ensuring seamless integration across diverse system requirements. It includes a high-precision 3.3V MHz XTAL oscillator embedded within the pad ring, enhancing timing accuracy and system stability. The library is optimized for a wide range of protocols, including RGMII, eMMC, ONFI, SPI, QSPI, LVCMOS, LPDDR, DDC, CEC, and SMBus, providing maximum flexibility for modern SoC designs. Built for robust reliability, it meets stringent 2kV HBM and 500V CDM ESD protection standards, ensuring resilience against electrostatic discharge events.
Operating Conditions
| Feature | Value |
| Core Device | 1.8V |
| I/O Device | 1.8V Standard |
| Tj | -40C to 125C |
| ESD | 2kV HBM, 500V CDM |
Cell Names
| Cell Name | Cell Type |
| TG_IO_NS | Standard 150MHz I/O, w/ N/S Poly |
| TG_IO_EW | Standard 150MHz I/O, w/ E/W Poly |
Standards
- RGMII
- eMMC
- ONFI
- SPI
- QSPI
- LVCMOS
- LPDDR
- DDC
- CEC
- SMBus
