Flash controller IP

The SPI Flash Controller Verification IP (VIP) is a powerful tool for verifying and simulating SPI Flash memory controllers in SoCs. It supports single, dual, and quad SPI modes, enabling seamless validation of read, write, erase, and advanced operations.
This VIP is designed for diverse applications, including IoT devices, automotive systems, consumer electronics, and aerospace. It ensures efficient performance, low power usage, and reliable integration of SPI Flash memory in mission-critical and everyday devices

The NAND Flash Controller Verification IP (VIP) is a specialized tool for validating and simulating NAND Flash memory interfaces in System-on-Chip (SoC) designs. It ensures compliance with protocols, error correction, and optimal performance across varied conditions.
This versatile tool supports a wide range of applications, including automotive, consumer electronics, industrial automation, and aerospace. By guaranteeing reliable integration of NAND Flash memory, it enables seamless functionality in devices ranging from gaming consoles to mission-critical systems

Compliant with Flash Devices from major Flash Device Vendors.
Full Flash with SPI Master Functionality.
Supports 3 modes of operation
Slave Mode - Accessing flash device through CSR registers from SOC Slave interface

ONFI v5.0 compliant + Up to 2.4GByte/s.
All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between

The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips.
It is designed with scalability in mind and provides standard AXI interface for the ease of integration in SoC design.
The NFC has many configurable features to support the requirements for different NAND Flash applications.

Supports access to one data memory and one information memory.
Optionally supports redundancy.
Optional ECC support with SECDEC (single-bit error correction, double-bit error detection).
Programmable read/write timings, to support different clock frequencies.

The AHB Parallel Flash Controller allows an AHB Master component (usually a CPU) to read, program, or erase the connected arrangement of external parallel SuperFlash devices.
The controller implements a set of configuration registers on an APB interface, while Flash accesses occur via an AHB interface. It also implements several modes of operation to facilitate these functions.

Set of software accessible control registers to execute any Flash memory command
Supports any device clock frequency, polarity and phase,
Programmable baud rate generator,
Built in FLASH Commands decoder supports most popular FLASH devices,

Flash Controller IP