ONFI 3.2 NAND Flash Controller IP Compliant to JEDEC

The ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, a synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, and others.

The ONFI 3.2 NAND Flash Controller IP core includes a host of configuration options from page size to band selects. The controller offers Hamming Code (1bit error correction and 2bit error detection) and Arasan’s patent pending BCH (option for 4-, 8-, 12- and 64-bit error correction or more.) error code correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash. The IP core supports the Open NAND Flash Interface Working Group (ONFI) 3.2 standard and is backward compatible. It uses differential signaling on the clock and data lines and clocks at any frequency up to 200 MHz.

ONFI 3.2 NAND Flash controller supports a variety of host bus interfaces for easy adoption into any design architecture. An optional ONFI software stack and driver for Linux is available to shorten engineers’ development time and efforts features.

ONFI 3.2 improves on version ONFI 3.1 with more robust power sequencing to protect NAND flash, more flexible timing to support NAND usage in different topologies, improved parameters for testing, and other enhancements.

• Supports ONFI 3.2 and backward compatible to ONFI 3.0, 2.3, 1.0
• Asynchronous SDR
• Up to 533 MT/s high performance with patent-pending ECC engine with code-length configurable BCH coder and decoder
• Proven and robust high performance ONFI 3.2 NV-DDR2 PHY delivered in RTL with synthesizable DLL/PLL
• I/O pads compatible to ONFI 3.2 266MHz NV-DDR2 operation at 1.8v or 3.3v
• Optionally, a hardened ONFI 3.2 PHY delivered in GDSII including DLL and PLL is available
• Offered as a Total IP solution including RTL Host Controller IP, Verification IP, Software Stack, and Hardware Development Platform

• Compliant to ONFI 3.2 Specification
• Supports SDR, NV-DDR and NV-DDR2
• Included synthesizable PLL/DLL
• ONFI 3.2 compatible 1.8v NV-DDR2 I/O pads supporting up to 533MT/s is available
• Supports SLC and MLC devices
• Supports memories up to 128Gb
• Support Radiation hardening [defence, space, nuclear applications etc.]
• Supports differential signaling on clock and data lines
• Supports warm up cycles for high-speed operation
• Supports all mandatory commands and selected optional commands

• Fully compliant core
• Premier direct support from Arasan IP core designers
• Easy-to-use industry standard test environment
• Unencrypted source code allows easy implementation
• Reuse Methodology Manual guidelines (RMM) compliant Verilog code ensured using Spyglass

• RMM Compliant Synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents