DRAM IP
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509
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55
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10)
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Low Latency DRAM Synthesizable Transactor
- Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specifications
- Supports 8 internal banks
- Supports all mode registers programming
- Supports programmable read latency and row cycle time
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Low Latency DRAM Memory Model
- Supports Low Latency DRAM memory devices from all leading vendors.
- Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specification.
- Supports programmable clock frequency of operation.
- Supports 8 internal banks.
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SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application;
- SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 40um * 270um with DUP stagger bonding pads;
- Work IO voltage: 1.2V/1.5V/1.8V;
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SMIC 55nm LL LPDDR interface for DRAM application
- LPDDR interface for DRAM application;
- SMIC 55nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 35um * 174um with DUP stagger bonding pads;
- Work voltage: 1.8V;
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SMIC 65nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application
- SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application;
- SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) (35~80)um * 211um with DUP stagger bonding pads;
- Work voltage: 1.8V/2.5V/3.3V;
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SMIC 65nm LL SSTL_18/SSTL_2/LPDDR/LVTTL COMBO interface for DRAM application
- SSTL_18/SSTL_2/LPDDR/LVTTL COMBO interface for DRAM application;
- Support ONFI3.1/Toggel 2.0 interface application;
- SMIC 65nm Logic Low Leakage Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 35um * 325um with DUP stagger bonding pads;
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SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application
- SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application;
- 2).Suppport ONFI3.1/Toggle2.0 interface;
- 3).SMIC 55nm Logic Low Leakage Salicide 1.2V/1.8V/2.5V Process;
- 4).Cell Size (Width * height) 35um * 325um with DUP stagger bonding pads;
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Embedded OTP (One-Time Programmable) IP, 2Kx32 bits for 1.0V/2.6V DRAM
- Logic Embedded IP
- Programming NeoFuse cell by using quantum tunneling mechanism
- High yield performance
- Small IP size