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DDR memory controller IP

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Compare 334 IP from 35 vendors (1 - 10)
  • LPDDR5X DDR Memory Controller
    • JEDEC LPDDR5X/LPDDR5 devices compatible
    • Data rates up to 8533Mbps
    • Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
    Block Diagram -- LPDDR5X DDR Memory Controller
  • Avalon Mobile DDR Memory Controller
    • 200 MHz Cyclone / Stratix memory performance
    • Supports all standard Mobile DDR SDRAM devices
    • 1 to 16 Avalon® independent local bus port interfaces
    • Avalon Pipelined and Burst transfers
    Block Diagram -- Avalon Mobile DDR Memory Controller
  • DO-254 DDR Memory Controller 1.00a
    • DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support
    • Up to 800 Mb/s (400 MHz double data rate) performance
    • Up to four MCB cores in a single Spartan-6 device
    • Configurable dedicated multi-port user interface to FPGA logic
  • DDR Memory Controller IP for low power and high reliability
    • Supports DDR protocol standard JESD79F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR commands as per the specs. Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • High Performance DDR 3/2 Memory Controller IP
    • Supports DDR3/DDR2 SDRAM
    • 16 bits width DDR2/DDR3 SDRAM Interface
    • Memory Clock up to 462MHz, DFI Clock up to 462MHz
    • Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
  • DDR 4/3 Memory Controller IP - 2400MHz
    • Support s DDR 4 /DDR3 SDRAM
    • 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
    • 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
    • Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
    Block Diagram -- DDR 4/3 Memory Controller IP - 2400MHz
  • High quality video decoder IP Core with 3D comb filter and supporting fixed rate sampling
    • Broadcast quality video decoder IP core.
    • Supports all NTSC and PAL video standards as well as SECAM.
    • Fixed rate or line-locked sampling.
  • LPDDR5/4X PHY IP for TSMC
    • Application-optimized configurations for fast time to delivery and lower risk
    • Memory controller interface complies with DFI standard up to 5.0
    • Internal and external datapath loop-back modes
    • Per-bit deskew on read and write datapath
  • DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
    • Compliant with JEDEC standard for LPDDR5/4/3, DDR4/3
    • DRAM rank of up to 4
    • Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
    • Support for dynamic DRAM frequency scaling
    Block Diagram -- DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
  • LPDDR5X/5/4X/4 Memory Controller IP
    • Intensive DRAM Utilization
    • Ultra Low Power Consumption
    • Extremely Low Latency
    • Safety & Security
    Block Diagram -- LPDDR5X/5/4X/4 Memory Controller IP
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