How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
T2M GmbH
Category:
DDR
DDR Memory Controller IP for low power and high reliability
DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Sp…
Overview
DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Specification Compliant. Through its DDR compatibility, it provides a simple interface to a wide range of low-cost devices. DDR IP is proven in FPGA environment. The host interface of the DDR can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
Key features
- Supports DDR protocol standard JESD79F Specification.
- Compliant with DFI-version 2.0 or higher Specification.
- Supports all the DDR commands as per the specs. Supports up to 16 AXI ports with data width upto 512 bits.
- Supports controllable outstanding transactions for AXI write and read channels
- Supports in port arbitration and multi port arbitration.
- Supports user programmable page policy.
- Supports Error Checking and correction (ECC).
- Supports retry on ECC error, with retry limit user controllable.
- Supports high clock speeds in ASIC and FPGA. Supports low latency for write and read path. Supports reordering of transactions for higher performance.
- Supports all device speeds as per specification. Supports Programmable CAS latency.
- Supports Programmable burst lengths: 2,4 and 8. Supports Write data Mask.
- Supports the X4, X8, X16 devices.
- Supports the 64MB, 128MB, 256MB, 512MB, 1GB memory densities.
- Supports the following burst types.
- Supports burst order.
- Supports for All Mode registers programming. Supports for Extended Mode registers
- programming.
- Supports Auto refresh & self refresh modes.
- Supports Auto precharge option for each burst access.
- Supports Power Down features.
- Supports input clock stop and frequency change. Supports DLL operation.
- Fully synthesizable
- Static synchronous design.
- Positive edge clocking and no internal tri-states. Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
What’s Included?
- The DDR interface is available in Source and netlist products.
- The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package Documentation contains User's Guide and Release notes.
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
DDR Controller IP
Vendor
T2M GmbH
Provider
T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets.
T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules.
With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
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Frequently asked questions about DDR Controller IP cores
What is DDR Memory Controller IP for low power and high reliability?
DDR Memory Controller IP for low power and high reliability is a DDR IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.