DFSPI – SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption) + … NOR & NAND Flash Memory Support
Need high-speed, low-pin-count access to HyperRAM™? Our new IP Core supports HyperBus™ and xSPI (JESD251A) protocols, delivering up to 200 MHz performance with full AXI, AHB, and APB compatibility.
- HyperRAM™-ready
- OCTAL SPI master/slave
- DMA support
- Fully configurable & FPGA/ASIC-friendly
Perfect for embedded and SoC designs needing fast, reliable PSRAM control — backed by DCD-SEMI’s trusted IP quality.
Unlock PSRAM Performance with DCD-SEMI’s HyperBus™ Memory Controller IP Core
DCD-SEMI introduces its latest IP Core innovation — a high-performance, HyperBus™-compatible controller purpose-built to meet the needs of PSRAM users. Based on our proven DFSPI architecture, this IP core enables reliable, high-speed communication with HyperRAM™ devices, delivering the bandwidth and responsiveness required by today’s memory-hungry embedded systems.
Designed for straightforward integration, the controller supports AXI, AHB, and APB bus interfaces and offers full compatibility with xSPI (JESD251A) and the HyperBus™ memory protocol. Whether you’re developing an SoC or FPGA-based design, this IP core makes it easy to interface with modern PSRAM technologies while maintaining a low-pin-count footprint and simplified routing.
Why to choose DCD-SEMI:
- HyperBus™ & xSPI protocol support – Fully compatible with HyperRAM™ devices
- Up to 200 MHz clock speed – Delivers the throughput PSRAM applications demand
- AXI, AHB, and APB interface support – Easy fit for modern architectures
- Flexible SPI modes – SINGLE, DUAL, QUAD, and OCTAL SPI master/slave options
- Customizable timing & SCK parameters – Tweak for maximum PSRAM performance
- DMA integration – For efficient high-speed memory access
- Technology-independent HDL – Easily portable across FPGA and ASIC platforms
This IP core is a drop-in solution for developers looking to boost system performance with HyperRAM™/PSRAM, offering ease of use, configurability, and the trusted reliability of DCD-SEMI’s IP design. Whether you’re building an embedded device or a complex SoC, our HyperBus™ Memory Controller provides the speed and flexibility you need.
DCD-SEMI’s advanced HyperBus™ Memory Controller IP Core is a versatile, high-performance solution designed for seamless integration into modern SoCs and FPGA-based systems. Based on our proven DFSPI architecture, this controller bridges easily to APB, AHB, and AXI buses and supports SINGLE, DUAL, QUAD, and OCTAL SPI master/slave modes — making it ideal for a wide range of embedded applications.
This fully configurable SPI controller includes optional support for the HyperBus™ memory protocol and xSPI (Expanded Serial Peripheral Interface – JESD251A), enabling high-speed communication with the latest generation of HyperRAM™ and NOR/NAND Flash memories. The controller also features adjustable serial clock polarity and phase (SCK), ensuring compatibility with a broad array of SPI-based devices.