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DDR IP

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Compare 1,483 IP from 96 vendors (1 - 10)
  • Secure-IC's Securyzr(TM) DDR Encrypter
    • Protect the external memory
    • On-the-fly encryption
    • Optional authentication
    Block Diagram -- Secure-IC's Securyzr(TM) DDR Encrypter
  • DDR multiPHY IP
    • Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
    • When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
    • Scalable architecture that supports from 0 to 1066 Mbps
    • DFI 2.1 interface to controller
    Block Diagram -- DDR multiPHY IP
  • Gen 2 DDR multiPHY IP
    • Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR3-2133
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell components allows precise control of timing critical delay and skew paths
    Block Diagram -- Gen 2 DDR multiPHY IP
  • Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
  • DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
  • DDR Secure Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Secure Controller supporting DDR5
  • DDR Low Latency Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Low Latency Controller supporting DDR5
  • DDR Controller supporting DDR5 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with Advanced Features Package
  • DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
  • DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
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