Ddr IP

Compare 1,723 IP from 100 vendors (1 - 10)

800Mb/s DDR DLL on TSMC CLN55LP
- Generates precise degrees of clock phase shifting for mobile or standard DDR applications
- Phase adjustments of non-continuous strobe clocks
- Compensates for external clock and data delays
- Programmable delay for precise and granular control of delay
DDR Synthesizable Transactor
- Supports 100% of DDR protocol standard JESD79F
- Supports all the DDR commands as per the specs
- Supports all device speeds as per specification
- Supports programmable CAS latency
DDR DFI Verification IP
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR Applies to :
- DDR protocol standard JESD79F Specification
- Supports all Interface Groups.
DDR Memory Model
- Supports DDR memory devices from all leading vendors.
- Supports 100% of DDR protocol standard JESD79F.
- Supports all the DDR commands as per the specs.
- Supports all device speeds as per specification.
DDR Assertion IP
- Specification Compliance
- Quickly validates the implementation of the DDR standard
- Checks for following
- Check-points include power on, Initialization and power off rules,
DDR Controller IIP
- Supports DDR protocol standard JESD79F Specification.
- Compliant with DFI-version 2.0 or higher Specification.
- Supports all the DDR commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
DDR DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR Applies to :
- DDR protocol standard JESD79F Specification
DDR Controller
- Sideband and in-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
- Memory controller interface complies with DFI standards up to version 5.0
- Priority per command on Arm^® AMBA^® 4 AXI, AMBA 3 AXI
- Single and multi-port host interface options
- QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
- Silicon proven and shipping in volume
DDR and LPDDR Combo PHY
- Supports multiple combinations of DDR/LPDDR interfaces
- Compliant with JEDEC DDR and LPDDR standards
- Supports all auto calibrations
- Industry leading area and power
DDR multiPHY IP
- Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
- When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
- Scalable architecture that supports from 0 to 1066 Mbps
- DFI 2.1 interface to controller

DDR IP