Ddr IP

Compare 1,698 IP from 98 vendors (1 - 10)

AMBA AHB Bus to DDR SDRAM Controller
- External pin reduction by transferring 2 bits of data per pin.
- Supports multiple external SDRAM banks.
- Automatic refresh generation with programmable refresh intervals.
- Self-refresh mode to reduce system power consumption.
- Standard delay cells or user provided DLL for DQ and DQS alignment.
DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP
- The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM
- The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA IP core work in conjunction with the ALTMEMPHY physical interface IP function
- The controllers offer a half-rate interface and a full-rate interface to the customer application logic
- For exact device support, please refer to the user guide.
DDR and DDR2 SDRAM Controller Intel® FPGA IP Core
- The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals
- The controllers translate read-and-write requests from the local interface into all the necessary SDRAM command signals.
800Mb/s DDR DLL on TSMC CLN55LP
- Generates precise degrees of clock phase shifting for mobile or standard DDR applications
- Phase adjustments of non-continuous strobe clocks
- Compensates for external clock and data delays
- Programmable delay for precise and granular control of delay
DDR Synthesizable Transactor
- Supports 100% of DDR protocol standard JESD79F
- Supports all the DDR commands as per the specs
- Supports all device speeds as per specification
- Supports programmable CAS latency
DDR DFI Verification IP
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR Applies to :
- DDR protocol standard JESD79F Specification
- Supports all Interface Groups.
DDR Memory Model
- Supports DDR memory devices from all leading vendors.
- Supports 100% of DDR protocol standard JESD79F.
- Supports all the DDR commands as per the specs.
- Supports all device speeds as per specification.
DDR Assertion IP
- Specification Compliance
- Quickly validates the implementation of the DDR standard
- Checks for following
- Check-points include power on, Initialization and power off rules,
DDR Controller IIP
- Supports DDR protocol standard JESD79F Specification.
- Compliant with DFI-version 2.0 or higher Specification.
- Supports all the DDR commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
DDR DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR Applies to :
- DDR protocol standard JESD79F Specification

DDR IP