DDR DFI Verification IP

Overview

DDR DFI Verification IP provides an smart way to verify the DDR DFI component of a SOC or a ASIC. The SmartDV's DDR DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.

DDR DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with DFI version 2.0 or higher Specification.
DFI-DDR Applies to :
- DDR protocol standard JESD79F Specification
Supports all Interface Groups.
Supports Write Transactions with Data mask.
Supports Read data burst interruption
Supports DRAM Clock disabling feature.
Supports Data bit enable/disable feature.
Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
Supports frequency change protocol.
Supports Low power control features.
Supports Error signaling.
Supports DFI Read/Write Chip Select.
Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays Constantly monitors DFI behavior during simulation.
Protocol checker fully compliant with DFI version 2.0 or higher Specification.
Bus-accurate timing for min, max and typical values.
Notifies the test bench of significant events such as transactions, warnings
Built in functional coverage analysis.
Supports callbacks, so that user can access the data observed by monitor.

Benefits

Faster test bench development and more complete verification of DDR DFI designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the DDR DFI testcases.
Complete UVM/OVM sequence library for DDR DFI controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all classes, tasks and functions used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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