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Audio Sample Rate Converter
- The ASRC core is a compact and high-performance audio sample rate converter.
- It accurately converts digital audio signals between different sample rates while maintaining signal integrity and minimizing distortion.
- Supporting both asynchronous and synchronous conversion modes, the low latency ASRC can be used in real-time streaming applications as well as in high-speed batch processing environments.
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General-Purpose I/O Controller with APB Interface
- User selectable number of GPIO signals from 1 to 32
- All GPIO signals can be bi-directional (external bi-directional I/O cells are required in that case)
- All GPIO signals can be tri-stated or open-drain enabled (external tri-state or open-drain I/O cells are required in that case)
- GPIO signals programmed as inputs can cause an interrupt request to the CPU
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AVC/H.264 Video Encoder with Compressed Frame Store
- Low power AVC/H.264 encoder
- Small silicon footprint
- Optimized for low-latency
- Low-bit-rate video streaming
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MACsec Protocol Engine for 10/100/1000 Ethernet
- The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard.
- It supports all cipher suites provisioned by the MACsec standard and the VLAN-in-Clear improvement and is silicon- and performance-optimized for networks operating up to 1Gbps.
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Low-Power Deeply Embedded RISC-V Processor
- The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.
- It implements a single-issue, in-order, 5-stage execution pipeline, and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
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1G/10G TCP/IP Hardware Stack
- The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack.
- More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from — or even the presence of — a system processor.
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CANsec Acceleration Engine
- The CAN-SEC IP core implements a hardware accelerator for the CANsec extension of the CAN-XL protocol, as defined in CiA’s 613-2 specification.
- The CANsec specification provisions two ciphers with key lengths of 128, 192, or 256 bits to protect CAN XL frames’ payload, all of which are supported by the hardware accelerator.
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Ultra-Low-Power Deeply Embedded RISC-V Processor
- The BA51 is a highly configurable, low-power, deeply embedded RISC-V processor IP core.
- It implements a single-issue, in-order, 2-stage execution pipeline and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
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AXI Subsystem
- The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces such as the BA20, BA21, and several RISC-V Implementations.
- The AXI Subsystem combines peripheral and interface IP cores with drivers and other essential software and an AXI/APB bus infra- structure.
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AHB Subsystem
- The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus interfaces such as the BA22-DE, BA22-CE, ARM Cortex-M0/M0+/M1/M3/M4, and several RISC-V processors.
- The AHB subsystem is available in two versions
