IP Catalog > AMBA 5 CHI

AMBA 5 CHI IP

Filter
Filter
Search (16)
Compare 16 IP from 8 vendors (1 - 10)
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Coherent Mesh Network
    • High-Performance, Scalable Coherent Mesh
    • Reduce SoC Integration Time
    • Maximize Compute Density
    • Coherent Multichip Links
  • Tessent in-life monitoring
    • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
    • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
    • Status Monitors provides embedded logic analyzer capability
    • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • Tessent Automotive IC debug and optimization
    • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
    • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
    • Status Monitors provides embedded logic analyzer capability
    • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • Tessent AI IC debug and optimization
    • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
    • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
    • Status Monitors provides embedded logic analyzer capability
    • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • Tessent SoC debug and optimization
    • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
    • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
    • Status Monitors provides embedded logic analyzer capability
    • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
    • Easy to integrate the NoC Silicon IP using interface
    • N master and M slave ports based on customer requirement
    • Supports wide range of memory map.
    Block Diagram -- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
  • FlexRay Controller
    • FlexRay Communications System Protocol Specification, Version 2.1, Revision A compliant protocol implementation
    • FlexRay Communications System Electrical Physical Layer Specification, Version 2.1, Revision A compliant bus driver interface
    • TUV conformance tested
    • Proven in Freescale's MFR43xx and MCP55xx devices
    Block Diagram -- FlexRay Controller
  • 5M pixel sensor support Image Signal Processing (ISP) IP
    • Defective Pixel Correction
    • Gb/Gr Unbalance Correction
    • 2D Lens-Shading Correction (8x6)
    Block Diagram -- 5M pixel sensor support Image Signal Processing (ISP) IP
  • Configurable UART with FIFO, software and hardware flow control
    • Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    Block Diagram -- Configurable UART with FIFO, software and hardware flow control
×
Semiconductor IP