NoC Silicon IP for RISC-V based chips supporting the TileLink protocol

Overview

Key Features

• Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.Any number of master and slave port is supported. Each port can be configured individually.AMBA AHB3-Lite,5; AMBA AXI 3, 4, 4-Lite,4-Stream, 5,5-Lite,5-Stream, AMBA APB 2,3,4,5 TileLink Tl-UL, Tl-UHConfigurable memory map for different access types of memory regions.Support for different protocol for master and slave port interface.Each port data width can be different. Apart from data, other protocol supported signal can also different width.Early response possibleSupport different phase shifteded frequencies for each Master and SlavesPort priority, Programmable register, Keeper countSupport physical address conversion through NOCWithin minimum latency req or rsp can propagate through NoCBoth little & high endianness is supportedInterleaving support, Out of order transfer , Exclusives supports in AXI portSecure TransferBeat TransferNon contiguous addressEnable bufferingArithmetic and logical transferBack to back transfer supports in AHB

Benefits

• Available in native Verilog (RTL).
• Unique development RTL coding technique to ensure the highest levels of quality for lower latency, highest throughput and lesser area.
• Synthesis & CDC are clean up.
• Verified with expert team using comprehensive and Regression Test Suites.
• Consistency of interface, installation, operation, and documentation across all our IPs
• 24X5 customer support
• Unique and customizable licensing models

Block Diagram

Deliverables

• NoC Matrix (Crossbar/Mesh) & NoC Port (AXI/AHB/APB/Tilelink)
• IP generator & config tool
• Verilog Test Environment with Verilog Testcases
• IP analysis reports
• Linting report
• Synthesis report
• IP-XACT RDL generated address map
• Simulation script
• IP Block Guide
• Quick Start Guide

Technical Specifications