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"text_low_priority" => "The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). ARC processor families support a broad portfolio certified audio codecs post-processing software from range popular standards including Dolby DTS Microsoft SRS.With patented configuration technology cores can be easily customized to meet any application requirement ultra-small task-specific controllers robust processors. Additionally extendible instruction set makes it possible for customers add instructions operations provide additional acceleration more efficient operation resulting in highly differentiated designs that cannot built with standard off-the-shelf DSPs or CPUs.These also designed tolerant high memory latencies. Compared other solutions market impact latency load is negligible making best solution systems like video graphics IP where DDR shared resources.DSP-Enhanced Processors AudioThe family which includes EM5D EM7D EM9D EM11D specifically ultra low-power DSP applications. These enhanced ISA adds over 150 optimized area- code-efficient real-time ARCv2 RISC ISA. feature power-efficient unified 32x32 MUL/MAC unit fixed point vector single multiple data (SIMD) operations. EM features balanced 3-stage Harvard architecture pipeline provides throughput offer excellent control performance.ARC DSP-Enhanced HS45D HS47D than DSP-optimized delivering unique combination high-performance high-efficiency digital signal processing. To speed execution math functions give designers option implement hardware integer divider 64-bit multiply multiply-accumulate (MAC) addition subtraction optional IEEE 754-compliant floating (single- double-precision both). compatible ultra-low power have same easy migrate code between two families. Dual 32x16 XMAC component supports up MAC per all & dual 16x16 instructionsDual shifters 80-bit accumulators allow pseudo floating-point performed greatly expanded dynamic rangeRAM area powerImproved system efficiency ARM® AMBA® AXI™/AHB™ bus bridgesSynopsys XY Advanced delivers performance dedicated coresSynopsys ARCompact 16-/32-bit reduces size by 40 percent compared only setsDelivered as synthesizable RTL source (Verilog®) fully industry-standard design methodologies tool flowsXY MetaWare Development Toolkit xCAM nSIM simulators"
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<ul><li>32位精简指令（RISC）架构\r\n</li><li>16或32个通用寄存器\r\n</li><li>104条基本指令，10种寻址模式\r\n</li><li>可选的IEEE 754浮点运算单元（FPU）\r\n</li><li>最大支持74条用户自定义指令\r\n</li><li>5级流水线\r\n</li><li>可选内存保护单元（MPU）\r\n</li><li>可配置的指令和数据缓存（1 – 64kB，直接映射或者2/4路相连映射）\r\n</li><li>AMBA AXI或AHB核间互联总线，APB外设总线\r\n</li><li>可选用户态和特权态支持\r\n</li><li>最大32个中断向量，支持不可屏蔽中断（NMI）和系统调用\r\n</li><li>支持硬件中断嵌套，支持中断优先级\r\n</li><li>6-9个时钟周期的快速中断响应\r\n</li><li>支持JTAG和串口调试，可选硬件跟踪和性能统计计数器\r\n</li><li>最大4.12 CoreMark/MHz\r\n</li><li>多核支持\r\n</li><li>支持混合16位和32位指令，在不牺牲性能的情况下带来最大的代码密度\r\n</li><li>ASIC性能（以典型的28纳米制程为例）： \r\n</li><li>最大频率高至1GHz\r\n</li><li>最小逻辑门数目低至17000个\r\n</li><li>功耗比低至4uW/MHz\r\n</li><li>高质量的IP： \r\n</li><li>基于Verilog RTL\r\n</li><li>充分考虑测试，满足DFT的标准\r\n</li><li>经过量产检验的质量保证\r\n</li><li>提供免授权费的C/C++程序开发环境，基于业界标准的Eclipse IDE\r\n</li><li>很容易迁移到不带缓存的IP版本</li></ul>
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<p>The eSi-3250 32-bit CPU is targeted specifically for applications with high performance requiring caching, due to the use of slow on-chip memories such as eFlash, off-chip memories, or core/bus ratios greater than 1.<br />\r\n<br />\r\nThe processor features separate instruction and data caches that can be configured in size (from 1- 64kB) and associativity (direct mapped, 2 or 4-way associative) to increase performance and reduce power. The optional paged memory management unit (MMU) enables the implementation of virtual memory or memory protection. The 5-stage pipeline allows GHz clock frequencies to be achieved.<br />\r\n<br />\r\nThe eSi-3250’s instruction set includes everything you would expect in a high-performance processor. There are a number of optional application specific instructions and addressing modes. For example, a set of IEEE-754 compliant single-precision floating point instructions are available. Integer arithmetic instructions include a full 64 multiply and accumulate and divide. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. 32-bit SIMD instructions with 16-bit elements exploit data parallelism and reduce loop counts. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.<br />\r\n<br />\r\nFor those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented.<br />\r\n<br />\r\nInstructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and improving cache performance.<br />\r\n<br />\r\nThe processor supports both user and supervisor operating modes, with privileged instructions and memory areas, to allow an O/S kernel to be fully protected from user applications.<br />\r\n<br />\r\nHardware debug facilities include hardware breakpoints, watchpoints, trace, performance counters, null pointer detection and single-stepping for fast debugging of ROM, FLASH and RAM based programs.</p>
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eSi-3250面向高性能需要缓存的应用场景。这些场景往往使用了慢速的片上内存（比如eFlash）或片外内存，或者CPU核频率大于总线频率。<br />\r\n这枚处理器支持分离的指令和数据缓存。可以配置为1 – 64kB大小还可以配置为直接映射或者2/4路相连以增强性能降低功耗。 可选的带分页管理的内存管理单元（MMU）支持实现虚拟内存和内存保护。 其内部的5级流水线设计能有效的支持高达1GHz的时钟频率。<br />\r\neSi-3250的指令集基本包含了常见的高性能处理器中的所有指令。 它同时提供一系列的应用场景可选指令和寻址模式。 比如IEEE-754单精度浮点指令。 整型算术指令支持64位乘除和累乘。 支持位操作指令，比如位提取，位插入，clz，popcnt，ffs和位翻转等。 支持整数平方根，绝对值，min/max，crc和partiy指令。 支持32位SIMD引擎，操作两路16位数据，有效的提高并行度，减小循环次数。 Wait-for-interrupt指令允许快速的进入低功耗状态，支持对时钟频率和功耗进行限制。<br />\r\n对于那些需要极高的性能或者极低的功耗的场景，可以通过用户自定义指令和寄存器来支持实现。<br />\r\n同时支持16位和32位指令编码，常用的指令都有16位编码，最大程度的提高代码密度，提高缓存的命中。<br />\r\n同时支持用户态和核心态，特权指令和内存保护可以通过可选的MPU实现，操作系统可以跟应用程序有效隔离，从而得到充分的保护<br />\r\n硬件调试支持硬件断点，观察点，跟踪，性能计数器，空指针探测，单步。这些特性可以有效的支撑对运行在ROM，FLASH和RAM上的程序进行快速调试。<br />
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<ul>\r\n\t<li>32-bit RISC architecture</li>\r\n\t<li>16 or 32 general purpose registers</li>\r\n\t<li>104 basic instructions and 10 addressing modes</li>\r\n</ul>
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The eSi-3250 32-bit CPU is targeted specifically for applications with high performance requiring caching due to the use of slow on-chip memories such as eFlash off-chip or core/bus ratios greater than 1.\r\n\r\nThe processor features separate instruction and data caches that can be configured in size (from 1- 64kB) associativity (direct mapped 2 4-way associative) increase reduce power. optional paged memory management unit (MMU) enables implementation virtual protection. 5-stage pipeline allows GHz clock frequencies achieved.\r\n\r\nThe eSi-3250’s set includes everything you would expect a high-performance processor. There are number application specific instructions addressing modes. For example IEEE-754 compliant single-precision floating point available. Integer arithmetic include full 64 multiply accumulate divide. Bit manipulation bitfield extract insert count leading zeros population find first bit reverse included. square root absolute value min/max CRC parity also SIMD 16-bit elements exploit parallelism loop counts. Wait-for-interrupt allow fast entry low power states enabling gating.\r\n\r\nFor those require extreme ultra operation user-defined registers implemented.\r\n\r\nInstructions encoded either 16 32-bits all commonly used being 16-bits maximizing code density improving cache performance.\r\n\r\nThe supports both user supervisor operating modes privileged areas an O/S kernel fully protected from applications.\r\n\r\nHardware debug facilities hardware breakpoints watchpoints trace counters null pointer detection single-stepping debugging ROM FLASH RAM based programs. \r\n\t32-bit RISC architecture\r\n\t16 32 general purpose registers\r\n\t104 basic 10 modes\r\n\tOptional IEEE 754 (FPU)\r\n\tSupports up 74 instructions\r\n\t5-stage pipeline\r\n\tOptional (MMU)\r\n\tConfigurable (1-64kB direct 4 way associative)\r\n\tAMBA AXI AHB interconnect APB peripheral bus\r\n\tUser modes\r\n\tUp vectored interrupts plus NMI system call\r\n\tHW nested prioritizable interrupts\r\n\tFast interrupt response time 6-9 cycles\r\n\tJTAG serial counters\r\n\tUp 4.12 CoreMark per MHz\r\n\tMultiprocessor support\r\n\tIntermixed result exceptional without compromising performance\r\n\tASIC (Typical 28nm):\r\n\tUp 1 GHz\r\n\tFrom 17k gates\r\n\tFrom 4uW/MHz\r\n\tHigh quality IP:\r\n\tVerilog RTL\r\n\tDFT ready\r\n\tSilicon proven\r\n\tC C++ software development using license-free toolchain under industry standard Eclipse IDE\r\n\tEasy migration path cacheless version\r\n
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<ul><li>32位精简指令（RISC）架构\r\n</li><li>16或32个通用寄存器\r\n</li><li>104条基本指令，10种寻址模式\r\n</li><li>可选的IEEE 754浮点运算单元（FPU）\r\n</li><li>最大支持74条用户自定义指令\r\n</li><li>5级流水线\r\n</li><li>可选内存保护单元（MPU）\r\n</li><li>AMBA AXI或AHB核间互联总线，APB外设总线\r\n</li><li>可选用户态和特权态支持\r\n</li><li>最大32个中断向量，支持不可屏蔽中断（NMI）和系统调用\r\n</li><li>支持硬件中断嵌套，支持中断优先级\r\n</li><li>6-9个时钟周期的快速中断响应\r\n</li><li>支持JTAG和串口调试，可选硬件跟踪和性能统计计数器\r\n</li><li>最大4.12 CoreMark/MHz\r\n</li><li>支持多核\r\n</li><li>支持混合16位和32位指令，在不牺牲性能的情况下带来最大的代码密度\r\n</li><li>ASIC性能（以典型的28纳米制程为例）： \r\n</li><li>最大频率高至1GHz\r\n</li><li>最小逻辑门数目低至15000个\r\n</li><li>功耗比低至4uW/MHz\r\n</li><li>高质量的IP： \r\n</li><li>基于Verilog RTL\r\n</li><li>充分考虑测试，满足DFT的标准\r\n</li><li>经过量产检验的质量保证\r\n</li><li>提供免授权费的C/C++程序开发环境，基于业界标准的Eclipse IDE\r\n</li><li>迁移到16位IP或者带缓存的32位IP非常的容易</li></ul>
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<p>The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores. It is targeted specifically for low-power applications that require more computational power or a larger address space than is provided by the 16-bit eSi-1600 and that are able to be implemented using on-chip memory.<br />\r\n<br />\r\nThe cacheless memory architecture of the eSi-3200 allows for deterministic performance, making it particularly suitable for hard real-time control applications. It uses a modified-Harvard memory architecture allowing for simultaneous instruction and data fetch. The 5-stage pipeline allows GHz clock frequencies to be achieved.<br />\r\n<br />\r\nThe eSi-3200’s instruction set includes everything you would expect in a high-performance processor. There are a number of optional application specific instructions and addressing modes. A set of IEEE-754 compliant single-precision floating point instructions are available. Integer arithmetic instructions include a full 64 multiply and accumulate and divide. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. 32-bit SIMD instructions with 16-bit elements exploit data parallelism and reduce loop counts. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.<br />\r\n<br />\r\nFor those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented. Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and minimizing instruction fetch power consumption.<br />\r\n<br />\r\nThe processor supports both user and supervisor operating modes, with privileged instructions and memory areas via the optional MPU, to allow an O/S kernel to be fully protected from user applications.<br />\r\n<br />\r\nHardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and single stepping for fast debugging of ROM, FLASH and RAM based programs.</p>
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eSi-3200 32位CPU是eSi-RISC IP家族的中端处理器核。 它主要面向低功耗但是又要求一定算力或者较大的地址空间的应用场景。在这些场景下，16位处理器的地址空间通常不够用。这些地址空间可以通过片上内存来实现。<br />\r\n不带缓存的eSi-3200提供完全可预测的性能，这也使得它非常适合被应用到具有高实时性要求的控制场景。 它使用改进过的哈佛结构，同时支持取指令和取数据。 其内部的5级流水线设计能有效的支持高达1GHz的时钟频率。<br />\r\neSi-3200的指令集基本包含了常见的高性能处理器中的所有指令。 它同时提供一系列的应用场景可选指令和寻址模式。 还支持一系列的IEEE-754单精度浮点指令。 整型算术指令支持64位乘除和累乘。 支持位操作指令，比如位提取，位插入，clz，popcnt，ffs和位翻转等。 支持整数平方根，绝对值，min/max，crc和partiy指令。 支持32位SIMD引擎，操作两路16位数据，有效的提高并行度，减小循环次数。 Wait-for-interrupt指令允许快速的进入低功耗状态，支持对时钟频率和功耗进行限制。<br />\r\n对于那些需要极高的性能或者极低的功耗的场景，可以通过用户自定义指令和寄存器来支持实现。 同时支持16位和32位指令编码，常用的指令都有16位编码，最大程度的提高代码密度，缩小取指功耗。<br />\r\n同时支持用户态和核心态，特权指令和内存保护可以通过可选的MPU实现，操作系统可以跟应用程序有效隔离，从而得到充分的保护。<br />\r\n硬件调试支持硬件断点，观察点，跟踪，性能计数器，空指针探测，单步。这些特性可以有效的支撑对运行在ROM，FLASH和RAM上的程序进行快速调试。
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<ul><li>32位精简指令（RISC）架构\r\n</li><li>16或32个通用寄存器\r\n</li><li>104条基本指令，10种寻址模式\r\n</li><li>可选的IEEE 754浮点运算单元（FPU）\r\n</li><li>最大支持74条用户自定义指令\r\n</li><li>5级流水线\r\n</li><li>可选内存保护单元（MPU）\r\n</li><li>AMBA AXI或AHB核间互联总线，APB外设总线\r\n</li><li>可选用户态和特权态支持\r\n</li><li>最大32个中断向量，支持不可屏蔽中断（NMI）和系统调用\r\n</li><li>支持硬件中断嵌套，支持中断优先级\r\n</li><li>6-9个时钟周期的快速中断响应\r\n</li><li>支持JTAG和串口调试，可选硬件跟踪和性能统计计数器\r\n</li><li>最大4.12 CoreMark/MHz\r\n</li><li>支持多核\r\n</li><li>支持混合16位和32位指令，在不牺牲性能的情况下带来最大的代码密度\r\n</li><li>ASIC性能（以典型的28纳米制程为例）： \r\n</li><li>最大频率高至1GHz\r\n</li><li>最小逻辑门数目低至15000个\r\n</li><li>功耗比低至4uW/MHz\r\n</li><li>高质量的IP： \r\n</li><li>基于Verilog RTL\r\n</li><li>充分考虑测试，满足DFT的标准\r\n</li><li>经过量产检验的质量保证\r\n</li><li>提供免授权费的C/C++程序开发环境，基于业界标准的Eclipse IDE\r\n</li><li>迁移到16位IP或者带缓存的32位IP非常的容易</li></ul>
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<p>The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores. It is targeted specifically for low-power applications that require more computational power or a larger address space than is provided by the 16-bit eSi-1600 and that are able to be implemented using on-chip memory.<br />\r\n<br />\r\nThe cacheless memory architecture of the eSi-3200 allows for deterministic performance, making it particularly suitable for hard real-time control applications. It uses a modified-Harvard memory architecture allowing for simultaneous instruction and data fetch. The 5-stage pipeline allows GHz clock frequencies to be achieved.<br />\r\n<br />\r\nThe eSi-3200’s instruction set includes everything you would expect in a high-performance processor. There are a number of optional application specific instructions and addressing modes. A set of IEEE-754 compliant single-precision floating point instructions are available. Integer arithmetic instructions include a full 64 multiply and accumulate and divide. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. 32-bit SIMD instructions with 16-bit elements exploit data parallelism and reduce loop counts. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.<br />\r\n<br />\r\nFor those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented. Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and minimizing instruction fetch power consumption.<br />\r\n<br />\r\nThe processor supports both user and supervisor operating modes, with privileged instructions and memory areas via the optional MPU, to allow an O/S kernel to be fully protected from user applications.<br />\r\n<br />\r\nHardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and single stepping for fast debugging of ROM, FLASH and RAM based programs.</p>
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eSi-3200 32位CPU是eSi-RISC IP家族的中端处理器核。 它主要面向低功耗但是又要求一定算力或者较大的地址空间的应用场景。在这些场景下，16位处理器的地址空间通常不够用。这些地址空间可以通过片上内存来实现。<br />\r\n不带缓存的eSi-3200提供完全可预测的性能，这也使得它非常适合被应用到具有高实时性要求的控制场景。 它使用改进过的哈佛结构，同时支持取指令和取数据。 其内部的5级流水线设计能有效的支持高达1GHz的时钟频率。<br />\r\neSi-3200的指令集基本包含了常见的高性能处理器中的所有指令。 它同时提供一系列的应用场景可选指令和寻址模式。 还支持一系列的IEEE-754单精度浮点指令。 整型算术指令支持64位乘除和累乘。 支持位操作指令，比如位提取，位插入，clz，popcnt，ffs和位翻转等。 支持整数平方根，绝对值，min/max，crc和partiy指令。 支持32位SIMD引擎，操作两路16位数据，有效的提高并行度，减小循环次数。 Wait-for-interrupt指令允许快速的进入低功耗状态，支持对时钟频率和功耗进行限制。<br />\r\n对于那些需要极高的性能或者极低的功耗的场景，可以通过用户自定义指令和寄存器来支持实现。 同时支持16位和32位指令编码，常用的指令都有16位编码，最大程度的提高代码密度，缩小取指功耗。<br />\r\n同时支持用户态和核心态，特权指令和内存保护可以通过可选的MPU实现，操作系统可以跟应用程序有效隔离，从而得到充分的保护。<br />\r\n硬件调试支持硬件断点，观察点，跟踪，性能计数器，空指针探测，单步。这些特性可以有效的支撑对运行在ROM，FLASH和RAM上的程序进行快速调试。
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The eSi-3200 32-bit CPU is the mid-range member in eSi-RISC family of processor cores. It targeted specifically for low-power applications that require more computational power or a larger address space than provided by 16-bit eSi-1600 and are able to be implemented using on-chip memory.\r\n\r\nThe cacheless memory architecture allows deterministic performance making it particularly suitable hard real-time control applications. uses modified-Harvard allowing simultaneous instruction data fetch. 5-stage pipeline GHz clock frequencies achieved.\r\n\r\nThe eSi-3200’s set includes everything you would expect high-performance processor. There number optional application specific instructions addressing modes. A IEEE-754 compliant single-precision floating point available. Integer arithmetic include full 64 multiply accumulate divide. Bit manipulation such as bitfield extract insert count leading zeros population find first bit reverse can included. square root absolute value min/max CRC parity also SIMD with elements exploit parallelism reduce loop counts. Wait-for-interrupt allow fast entry low states enabling gating.\r\n\r\nFor those extreme ultra operation user-defined registers implemented. Instructions encoded either 16 32-bits all commonly used being 16-bits maximizing code density minimizing fetch consumption.\r\n\r\nThe supports both user supervisor operating modes privileged areas via MPU an O/S kernel fully protected from applications.\r\n\r\nHardware debug facilities hardware breakpoints watchpoints trace null pointer detection single stepping debugging ROM FLASH RAM based programs. \r\n\t32-bit RISC architecture\r\n\t16 32 general purpose registers\r\n\t104 basic 10 modes\r\n\tOptional IEEE 754 unit (FPU)\r\n\tSupports up 74 instructions\r\n\t5-stage pipeline\r\n\tOptional protection (MPU)\r\n\tAMBA AXI AHB interconnect APB peripheral bus\r\n\tOptional support modes\r\n\tUp vectored interrupts plus NMI system call\r\n\tHW nested prioritizable interrupts\r\n\tFast interrupt response time 6-9 cycles\r\n\tJTAG serial counters\r\n\tUp 4.12 CoreMark per MHz\r\n\tMultiprocessor support\r\n\tIntermixed result exceptional without compromising performance\r\n\tASIC (Typical 28nm):\r\n\tUp 1 GHz\r\n\tFrom 15k gates\r\n\tFrom 4uW/MHz\r\n\tHigh quality IP:\r\n\tVerilog RTL\r\n\tDFT ready\r\n\tSilicon proven\r\n\tC C++ software development license-free toolchain under industry standard Eclipse IDE\r\n\tEasy migration path version caches\r\n
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"overview" => "<p>The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). The DSP-enhanced ARC processor families support a broad portfolio of certified audio codecs and post-processing software from a range of popular standards including Dolby, DTS, Microsoft and SRS.</p><p>With patented configuration technology, the cores can be easily customized to meet any application requirement from ultra-small task-specific controllers robust application processors. Additionally, the extendible instruction set makes it possible for customers to add instructions and operations to provide additional acceleration and more efficient operation, resulting in highly differentiated designs that cannot be built with standard, off-the-shelf DSPs or CPUs.</p><p>These processors are also designed to be tolerant to high memory latencies. Compared to other solutions in the market, the impact of latency on the processor load is negligible, making the ARC processors the best solution for systems like video and graphics IP, where DDR memory is shared with other resources.</p><p>DSP-Enhanced ARC EMxD Processors for Audio</p><p>The ARC EMxD family, which includes the ARC EM5D processor, ARC EM7D processor, ARC EM9D processor, and EM11D processor, are specifically designed for ultra low-power embedded DSP applications. These processors are based on the enhanced ARCv2DSP ISA, which adds over 150 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP vector and single instruction multiple data (SIMD) operations. The ARC EM DSP family features a balanced 3-stage Harvard architecture pipeline that provides efficient throughput and the cores offer excellent real-time control and DSP performance.</p><p>ARC DSP-Enhanced HS4xD Processors for Audio</p><p>The HS45D and HS47D processors support more than 150 DSP-optimized instructions, delivering a unique combination of high-performance control and high-efficiency digital signal processing. To speed the execution of math functions, the HS4xD cores give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a optional IEEE 754-compliant floating point unit (single- or double-precision or both). The ARC HS4xD processors are compatible with the ultra-low power ARC EMxD processors and have the same instruction set, making it easy to migrate code between the two processor families.</p>"
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eSi-3250面向高性能需要缓存的应用场景。这些场景往往使用了慢速的片上内存（比如eFlash）或片外内存，或者CPU核频率大于总线频率。<br />\r\n这枚处理器支持分离的指令和数据缓存。可以配置为1 – 64kB大小还可以配置为直接映射或者2/4路相连以增强性能降低功耗。 可选的带分页管理的内存管理单元（MMU）支持实现虚拟内存和内存保护。 其内部的5级流水线设计能有效的支持高达1GHz的时钟频率。<br />\r\neSi-3250的指令集基本包含了常见的高性能处理器中的所有指令。 它同时提供一系列的应用场景可选指令和寻址模式。 比如IEEE-754单精度浮点指令。 整型算术指令支持64位乘除和累乘。 支持位操作指令，比如位提取，位插入，clz，popcnt，ffs和位翻转等。 支持整数平方根，绝对值，min/max，crc和partiy指令。 支持32位SIMD引擎，操作两路16位数据，有效的提高并行度，减小循环次数。 Wait-for-interrupt指令允许快速的进入低功耗状态，支持对时钟频率和功耗进行限制。<br />\r\n对于那些需要极高的性能或者极低的功耗的场景，可以通过用户自定义指令和寄存器来支持实现。<br />\r\n同时支持16位和32位指令编码，常用的指令都有16位编码，最大程度的提高代码密度，提高缓存的命中。<br />\r\n同时支持用户态和核心态，特权指令和内存保护可以通过可选的MPU实现，操作系统可以跟应用程序有效隔离，从而得到充分的保护<br />\r\n硬件调试支持硬件断点，观察点，跟踪，性能计数器，空指针探测，单步。这些特性可以有效的支撑对运行在ROM，FLASH和RAM上的程序进行快速调试。<br />
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The eSi-3250 32-bit CPU is targeted specifically for applications with high performance requiring caching due to the use of slow on-chip memories such as eFlash off-chip or core/bus ratios greater than 1.\r\n\r\nThe processor features separate instruction and data caches that can be configured in size (from 1- 64kB) associativity (direct mapped 2 4-way associative) increase reduce power. optional paged memory management unit (MMU) enables implementation virtual protection. 5-stage pipeline allows GHz clock frequencies achieved.\r\n\r\nThe eSi-3250’s set includes everything you would expect a high-performance processor. There are number application specific instructions addressing modes. For example IEEE-754 compliant single-precision floating point available. Integer arithmetic include full 64 multiply accumulate divide. Bit manipulation bitfield extract insert count leading zeros population find first bit reverse included. square root absolute value min/max CRC parity also SIMD 16-bit elements exploit parallelism loop counts. Wait-for-interrupt allow fast entry low power states enabling gating.\r\n\r\nFor those require extreme ultra operation user-defined registers implemented.\r\n\r\nInstructions encoded either 16 32-bits all commonly used being 16-bits maximizing code density improving cache performance.\r\n\r\nThe supports both user supervisor operating modes privileged areas an O/S kernel fully protected from applications.\r\n\r\nHardware debug facilities hardware breakpoints watchpoints trace counters null pointer detection single-stepping debugging ROM FLASH RAM based programs. \r\n\t32-bit RISC architecture\r\n\t16 32 general purpose registers\r\n\t104 basic 10 modes\r\n\tOptional IEEE 754 (FPU)\r\n\tSupports up 74 instructions\r\n\t5-stage pipeline\r\n\tOptional (MMU)\r\n\tConfigurable (1-64kB direct 4 way associative)\r\n\tAMBA AXI AHB interconnect APB peripheral bus\r\n\tUser modes\r\n\tUp vectored interrupts plus NMI system call\r\n\tHW nested prioritizable interrupts\r\n\tFast interrupt response time 6-9 cycles\r\n\tJTAG serial counters\r\n\tUp 4.12 CoreMark per MHz\r\n\tMultiprocessor support\r\n\tIntermixed result exceptional without compromising performance\r\n\tASIC (Typical 28nm):\r\n\tUp 1 GHz\r\n\tFrom 17k gates\r\n\tFrom 4uW/MHz\r\n\tHigh quality IP:\r\n\tVerilog RTL\r\n\tDFT ready\r\n\tSilicon proven\r\n\tC C++ software development using license-free toolchain under industry standard Eclipse IDE\r\n\tEasy migration path cacheless version\r\n
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<ul><li>32位精简指令（RISC）架构\r\n</li><li>16或32个通用寄存器\r\n</li><li>104条基本指令，10种寻址模式\r\n</li><li>可选的IEEE 754浮点运算单元（FPU）\r\n</li><li>最大支持74条用户自定义指令\r\n</li><li>5级流水线\r\n</li><li>可选内存保护单元（MPU）\r\n</li><li>AMBA AXI或AHB核间互联总线，APB外设总线\r\n</li><li>可选用户态和特权态支持\r\n</li><li>最大32个中断向量，支持不可屏蔽中断（NMI）和系统调用\r\n</li><li>支持硬件中断嵌套，支持中断优先级\r\n</li><li>6-9个时钟周期的快速中断响应\r\n</li><li>支持JTAG和串口调试，可选硬件跟踪和性能统计计数器\r\n</li><li>最大4.12 CoreMark/MHz\r\n</li><li>支持多核\r\n</li><li>支持混合16位和32位指令，在不牺牲性能的情况下带来最大的代码密度\r\n</li><li>ASIC性能（以典型的28纳米制程为例）： \r\n</li><li>最大频率高至1GHz\r\n</li><li>最小逻辑门数目低至15000个\r\n</li><li>功耗比低至4uW/MHz\r\n</li><li>高质量的IP： \r\n</li><li>基于Verilog RTL\r\n</li><li>充分考虑测试，满足DFT的标准\r\n</li><li>经过量产检验的质量保证\r\n</li><li>提供免授权费的C/C++程序开发环境，基于业界标准的Eclipse IDE\r\n</li><li>迁移到16位IP或者带缓存的32位IP非常的容易</li></ul>
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<p>The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores. It is targeted specifically for low-power applications that require more computational power or a larger address space than is provided by the 16-bit eSi-1600 and that are able to be implemented using on-chip memory.<br />\r\n<br />\r\nThe cacheless memory architecture of the eSi-3200 allows for deterministic performance, making it particularly suitable for hard real-time control applications. It uses a modified-Harvard memory architecture allowing for simultaneous instruction and data fetch. The 5-stage pipeline allows GHz clock frequencies to be achieved.<br />\r\n<br />\r\nThe eSi-3200’s instruction set includes everything you would expect in a high-performance processor. There are a number of optional application specific instructions and addressing modes. A set of IEEE-754 compliant single-precision floating point instructions are available. Integer arithmetic instructions include a full 64 multiply and accumulate and divide. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. 32-bit SIMD instructions with 16-bit elements exploit data parallelism and reduce loop counts. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.<br />\r\n<br />\r\nFor those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented. Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and minimizing instruction fetch power consumption.<br />\r\n<br />\r\nThe processor supports both user and supervisor operating modes, with privileged instructions and memory areas via the optional MPU, to allow an O/S kernel to be fully protected from user applications.<br />\r\n<br />\r\nHardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and single stepping for fast debugging of ROM, FLASH and RAM based programs.</p>
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eSi-3200 32位CPU是eSi-RISC IP家族的中端处理器核。 它主要面向低功耗但是又要求一定算力或者较大的地址空间的应用场景。在这些场景下，16位处理器的地址空间通常不够用。这些地址空间可以通过片上内存来实现。<br />\r\n不带缓存的eSi-3200提供完全可预测的性能，这也使得它非常适合被应用到具有高实时性要求的控制场景。 它使用改进过的哈佛结构，同时支持取指令和取数据。 其内部的5级流水线设计能有效的支持高达1GHz的时钟频率。<br />\r\neSi-3200的指令集基本包含了常见的高性能处理器中的所有指令。 它同时提供一系列的应用场景可选指令和寻址模式。 还支持一系列的IEEE-754单精度浮点指令。 整型算术指令支持64位乘除和累乘。 支持位操作指令，比如位提取，位插入，clz，popcnt，ffs和位翻转等。 支持整数平方根，绝对值，min/max，crc和partiy指令。 支持32位SIMD引擎，操作两路16位数据，有效的提高并行度，减小循环次数。 Wait-for-interrupt指令允许快速的进入低功耗状态，支持对时钟频率和功耗进行限制。<br />\r\n对于那些需要极高的性能或者极低的功耗的场景，可以通过用户自定义指令和寄存器来支持实现。 同时支持16位和32位指令编码，常用的指令都有16位编码，最大程度的提高代码密度，缩小取指功耗。<br />\r\n同时支持用户态和核心态，特权指令和内存保护可以通过可选的MPU实现，操作系统可以跟应用程序有效隔离，从而得到充分的保护。<br />\r\n硬件调试支持硬件断点，观察点，跟踪，性能计数器，空指针探测，单步。这些特性可以有效的支撑对运行在ROM，FLASH和RAM上的程序进行快速调试。
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The eSi-3200 32-bit CPU is the mid-range member in eSi-RISC family of processor cores. It targeted specifically for low-power applications that require more computational power or a larger address space than provided by 16-bit eSi-1600 and are able to be implemented using on-chip memory.\r\n\r\nThe cacheless memory architecture allows deterministic performance making it particularly suitable hard real-time control applications. uses modified-Harvard allowing simultaneous instruction data fetch. 5-stage pipeline GHz clock frequencies achieved.\r\n\r\nThe eSi-3200’s set includes everything you would expect high-performance processor. There number optional application specific instructions addressing modes. A IEEE-754 compliant single-precision floating point available. Integer arithmetic include full 64 multiply accumulate divide. Bit manipulation such as bitfield extract insert count leading zeros population find first bit reverse can included. square root absolute value min/max CRC parity also SIMD with elements exploit parallelism reduce loop counts. Wait-for-interrupt allow fast entry low states enabling gating.\r\n\r\nFor those extreme ultra operation user-defined registers implemented. Instructions encoded either 16 32-bits all commonly used being 16-bits maximizing code density minimizing fetch consumption.\r\n\r\nThe supports both user supervisor operating modes privileged areas via MPU an O/S kernel fully protected from applications.\r\n\r\nHardware debug facilities hardware breakpoints watchpoints trace null pointer detection single stepping debugging ROM FLASH RAM based programs. \r\n\t32-bit RISC architecture\r\n\t16 32 general purpose registers\r\n\t104 basic 10 modes\r\n\tOptional IEEE 754 unit (FPU)\r\n\tSupports up 74 instructions\r\n\t5-stage pipeline\r\n\tOptional protection (MPU)\r\n\tAMBA AXI AHB interconnect APB peripheral bus\r\n\tOptional support modes\r\n\tUp vectored interrupts plus NMI system call\r\n\tHW nested prioritizable interrupts\r\n\tFast interrupt response time 6-9 cycles\r\n\tJTAG serial counters\r\n\tUp 4.12 CoreMark per MHz\r\n\tMultiprocessor support\r\n\tIntermixed result exceptional without compromising performance\r\n\tASIC (Typical 28nm):\r\n\tUp 1 GHz\r\n\tFrom 15k gates\r\n\tFrom 4uW/MHz\r\n\tHigh quality IP:\r\n\tVerilog RTL\r\n\tDFT ready\r\n\tSilicon proven\r\n\tC C++ software development license-free toolchain under industry standard Eclipse IDE\r\n\tEasy migration path version caches\r\n
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"overview" => "<p>The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). The DSP-enhanced ARC processor families support a broad portfolio of certified audio codecs and post-processing software from a range of popular standards including Dolby, DTS, Microsoft and SRS.</p><p>With patented configuration technology, the cores can be easily customized to meet any application requirement from ultra-small task-specific controllers robust application processors. Additionally, the extendible instruction set makes it possible for customers to add instructions and operations to provide additional acceleration and more efficient operation, resulting in highly differentiated designs that cannot be built with standard, off-the-shelf DSPs or CPUs.</p><p>These processors are also designed to be tolerant to high memory latencies. Compared to other solutions in the market, the impact of latency on the processor load is negligible, making the ARC processors the best solution for systems like video and graphics IP, where DDR memory is shared with other resources.</p><p>DSP-Enhanced ARC EMxD Processors for Audio</p><p>The ARC EMxD family, which includes the ARC EM5D processor, ARC EM7D processor, ARC EM9D processor, and EM11D processor, are specifically designed for ultra low-power embedded DSP applications. These processors are based on the enhanced ARCv2DSP ISA, which adds over 150 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP vector and single instruction multiple data (SIMD) operations. The ARC EM DSP family features a balanced 3-stage Harvard architecture pipeline that provides efficient throughput and the cores offer excellent real-time control and DSP performance.</p><p>ARC DSP-Enhanced HS4xD Processors for Audio</p><p>The HS45D and HS47D processors support more than 150 DSP-optimized instructions, delivering a unique combination of high-performance control and high-efficiency digital signal processing. To speed the execution of math functions, the HS4xD cores give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a optional IEEE 754-compliant floating point unit (single- or double-precision or both). The ARC HS4xD processors are compatible with the ultra-low power ARC EMxD processors and have the same instruction set, making it easy to migrate code between the two processor families.</p>"
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"text_low_priority" => "The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). ARC processor families support a broad portfolio certified audio codecs post-processing software from range popular standards including Dolby DTS Microsoft SRS.With patented configuration technology cores can be easily customized to meet any application requirement ultra-small task-specific controllers robust processors. Additionally extendible instruction set makes it possible for customers add instructions operations provide additional acceleration more efficient operation resulting in highly differentiated designs that cannot built with standard off-the-shelf DSPs or CPUs.These also designed tolerant high memory latencies. Compared other solutions market impact latency load is negligible making best solution systems like video graphics IP where DDR shared resources.DSP-Enhanced Processors AudioThe family which includes EM5D EM7D EM9D EM11D specifically ultra low-power DSP applications. These enhanced ISA adds over 150 optimized area- code-efficient real-time ARCv2 RISC ISA. feature power-efficient unified 32x32 MUL/MAC unit fixed point vector single multiple data (SIMD) operations. EM features balanced 3-stage Harvard architecture pipeline provides throughput offer excellent control performance.ARC DSP-Enhanced HS45D HS47D than DSP-optimized delivering unique combination high-performance high-efficiency digital signal processing. To speed execution math functions give designers option implement hardware integer divider 64-bit multiply multiply-accumulate (MAC) addition subtraction optional IEEE 754-compliant floating (single- double-precision both). compatible ultra-low power have same easy migrate code between two families. Dual 32x16 XMAC component supports up MAC per all & dual 16x16 instructionsDual shifters 80-bit accumulators allow pseudo floating-point performed greatly expanded dynamic rangeRAM area powerImproved system efficiency ARM® AMBA® AXI™/AHB™ bus bridgesSynopsys XY Advanced delivers performance dedicated coresSynopsys ARCompact 16-/32-bit reduces size by 40 percent compared only setsDelivered as synthesizable RTL source (Verilog®) fully industry-standard design methodologies tool flowsXY MetaWare Development Toolkit xCAM nSIM simulators"
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Powerful debug and non-intrusive real-time trace - Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
Memory Protection Unit (MPU) - Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
Integrated nested vectored interrupt controller (NVIC) - There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
Thumb-2 code density - On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
