IP Catalog > 16nm IO

16nm IO IP

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Search (73)
Compare 73 IP from 11 vendors (1 - 10)
  • General Purpose I/O (GPIO) in TSMC(12nm,16nm,22nm, 28nm, 40nm, 90nm BCD+, 152nm BCD, 180nm BCD)
    • Basic input/output unit for a chip with digital core
    • Consisting of driver, receiver & pull-up/down resistors
    • According to PAD arrangement, classified into two groups: Inline I/O & Stagger one.
    • M31 also develops fail-safe or tolerance I/O for special application. The leakage current is inhibited when I/O power ramp down (Diagram A).
  • M31 ESD I/O in TSMC 12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
    • High Density Library
    • Customized layout and function
    • Flexible cell combination
    • High ESD robustness analog cells
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • TSMC CLN16FF+GL 16nm IoT PLL - 30MHz-1000MHz
    • Optimized for very low power, running completely from core power supply.
    • Supports 32KHz reference clocks.
    • Extremely wide range of operation with multiplication factors over 8,000.
    • Small area, delivered as a single hard macro with guardrings and isolation.
  • TSMC CLN16FF+LL 16nm IoT PLL - 30MHz-1000MHz
    • Optimized for very low power, running completely from core power supply.
    • Supports 32KHz reference clocks.
    • Extremely wide range of operation with multiplication factors over 8,000.
    • Small area, delivered as a single hard macro with guardrings and isolation.
  • TSMC CLN16FFCLL 16nm IoT PLL - 30MHz-1000MHz
    • Optimized for very low power, running completely from core power supply.
    • Supports 32KHz reference clocks.
    • Extremely wide range of operation with multiplication factors over 8,000.
    • Small area, delivered as a single hard macro with guardrings and isolation.
  • 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
    • This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
    • The high-voltage GPIO is a flip-chip compatible 1.8V to 3.3V GPIO design, compliant with multiple I/O standards.
    • It comes as a macro cell with a pair of I/Os in each cell, allowing differential I/O interface capabilities as well.
    Block Diagram -- 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
  • 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
    • This library is a production-quality, silicon-proven I/O Library in TSMC 16nm technology.
    • The High Performance GPIO is a flip-chip compatible, 1.2V to 1.8V GPIO design, compliant with multiple high-speed Single-Ended and Differential I/O standards.
    • The macro cell comes as a pair of I/Os that can be configured as a differential I/O or two independent single- ended I/Os.
    Block Diagram -- 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
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