M31 ESD I/O in TSMC 12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
Overview
M31’s I/O Libraries now include integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O. We provide standard JEDEC ESD level and customized high-level ESD I/O across various process nodes.
Key Features
- High Density Library
- Customized layout and function
- Flexible cell combination
- High ESD robustness analog cells
Technical Specifications
Foundry, Node
12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
SMIC
Silicon Proven:
40nm
LL
,
55nm
LL
TSMC
Silicon Proven:
40nm
LP
UMC
Pre-Silicon:
28nm
HLP
Silicon Proven: 28nm HPC
Silicon Proven: 28nm HPC
Related IPs
- MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
- MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
- NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
- HDMI 2.0 TX PHY 6Gbps in TSMC (28nm, 16nm, 12nm)