Vendor:
Digital Core Design
Category:
SPI / QSPI XSPI
Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit micropr…
Overview
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors.
The DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DEMSCC also has facilities for modem control in both channels.
The user can configure the DEMSCC to handle all asynchronous formats regardless of data size, number of stop bits, or parity requirements. Control is done through the number of control and status registers for each channel separately. Within each operating mode, the DEMSCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
The DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DEMSCC also has facilities for modem control in both channels.
The user can configure the DEMSCC to handle all asynchronous formats regardless of data size, number of stop bits, or parity requirements. Control is done through the number of control and status registers for each channel separately. Within each operating mode, the DEMSCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
Key features
- Dual-Channel: A, B
- Configuration capability
- Asynchronous mode:
- Asynchronous (x16, x32, or x64 clock
- Isochronous (x1 clock)
- Character-Oriented mode:
- Monosynchronous
- Bisynchronous
- External Synchronous
- Bit-Oriented mode:
- SDLC/HDLC
- SDLC/HDLC Loop
- Complete status reporting capabilities
- Receiver data FIFO and Error FIFO
- SDLC Frame FIFO
- Transmitter FIFO
- Data encoderdecoder:
- NRZ, NRZI
- FM0, FM1
- Manchester (require external logic)
- Line break generation and detection
- Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Auto Echo
- Break, parity, overrun, framing error simulation
- Fully synchronous design with no internal tri-state buffers
- Transmission modes:
- Synchronous Byte (Bisync) features
- 5 to 8 Bit characters
- Programmable Sync character
- Transparent text mode operation
- Automatic Sync insertion during Idle
- Hardware CRC generation and detection
- CRC-16 or CRC-CCITT polynomials
- Asynchronous Features
- 5-8 Bits per character
- 1, 1,5, and 2 stop bits
- Break generation and detection
- Parity, overrun, and framing error detection
- Even, Odd or no parity
- Modem controls and indicators
- CTS and DCD lines, usable for modem control or user-defined input
- DTR and RTS usable for modem control or user-defined output
- Synchronous SDLC features
- 1-8 Bits character (transmitter)
- 5-8 Bits receiver character
- Hardware address recognition
- Automatic zero insertion and deletion
- I-Field residue handling
- Automatic flag insertion between messages
- Hardware CRC generation and reception
- Interrupt system features
- Channel functions and timers internally prioritized
- Channel functions and timers generate unique interrupt mode
- Prioritized Daisy-chain.
- LOOPBACK test mode
Benefits
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Global sales network
- Technology independence
- Professional service
- Getting a sillicon proven IP
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
DMESCC
Vendor
Digital Core Design
Type
Silicon IP
Provider
Digital Core Design
HQ:
Poland
Founded in 1999, Digital Core Design is a global leader in IP core development, specializing in microprocessor, microcontroller, and communication solutions. With a portfolio of over 100 IP cores, DCD continues to drive innovation in embedded systems, providing cutting-edge solutions for automotive, industrial, IoT, and security applications.
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is Enhanced Multiprotocol Serial Communication Controller?
Enhanced Multiprotocol Serial Communication Controller is a SPI / QSPI XSPI IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
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