256-steps adjustable delay cell
Overview
U40LPDLLDLYV1 is a 256-steps adjustable delay cell IP. It is based on UMC 40nm low power process.
Key Features
- Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
- Adjustable 8-bit delay steps, Maximum delay time 25.5ns, and Minimum delay time = 0.1ns (resolution: 0.1ns).
- Power Supply: Core power supply 1.1V
- Area : 600um ^2
Block Diagram
Technical Specifications
Foundry, Node
UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
Maturity
Available on request
Availability
Available
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