256-steps adjustable delay cell
Overview
U40LPDLLDLYV1 is a 256-steps adjustable delay cell IP. It is based on UMC 40nm low power process.
Key Features
- Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
- Adjustable 8-bit delay steps, Maximum delay time 25.5ns, and Minimum delay time = 0.1ns (resolution: 0.1ns).
- Power Supply: Core power supply 1.1V
- Area : 600um ^2
Block Diagram
Technical Specifications
Short description
256-steps adjustable delay cell
Vendor
Vendor Name
Foundry, Node
UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
Maturity
Available on request
Availability
Available
Related IPs
- Adjustable delay block for dual-phase regulator operation
- DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
- DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
- DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
- DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
- DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process