This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes. This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode. The C/D-PHY IP interfaces seamlessly to both D-PHY℠ and C-PHY℠ based sensors over its MIPI CSI-2® IP Core and MIPI Displays are increasingly adopting C-PHY over our MIPI DSI-2℠ IP core.
This combo PHY provides a low-power and high-performance interface for platforms ranging from processors to peripheral devices for mobile, automotive, AI, and IoT applications. It inter-operates seamlessly with Arasan Chip Systems CSI-2® and DSI-2℠, and offers built-in test capabilities including PRBS generator and internal loopback to support cost-effective tests for high volume manufacturing.
This combo PHY may be configured as either a D-PHY℠ with one clock and up to four data lanes, or a C-PHY℠ with up to 3 trio lanes. Area overhead to support both modes is minimized by reusing the D-PHY℠ blocks and high-speed IO’s.
