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XAUI PHY Intel® FPGA IP

Overview

The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Intel® FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

Key Features

  • Complete 10G Ethernet (XAUI) PHY solution for 4X 3.125 Gbps serial external interface
  • PHY consisting of 10GBASE-X physical coding sublayer (PCS), physical medium attachment (PMA), XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
  • Direct interface with Intel® FPGA 10GbE MAC for a complete solution
  • Direct standard XAUI PHY (4X 3.125 Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
  • PHY and soft XAUI PCS supported on many FPGA device families including: Stratix® IV, Stratix® V, Arria® V, and Arria® 10 FPGAs with serial transceivers
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various XAUI channel characteristics and devices in systems during operation
  • Implementing the Ethernet-standard XAUI PHY functions: data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4X 3.125 Gbps line, receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
  • Local serial loopback from transmitter to receiver at the device's serial transceiver for self-testing
  • High-performance internal system interfaces
    • Intel® FPGA Avalon® Streaming (Avalon-ST) SDR XGMII, 72-bit at 156.25 Mbps for data transfer
    • Intel® FPGA Avalon® Memory-Mapped (Avalon-MM) 32-bit for agent management

Block Diagram

XAUI PHY Intel® FPGA IP Block Diagram

Technical Specifications

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