Compute Express Link (CXL) FPGA IP

Overview

Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.

First FPGA to pass CXL Consortium Compliance Program (up to 32 GT/s speed).

CXL Protocol Hard IP Functionality Accelerates a Wide Range of Data-Centric Workloads

Accelerated Computing: CXL seamlessly connects FPGAs to accelerators and GPUs, enhancing performance in compute-intensive workloads like AI, machine learning, data analytics, and scientific simulations.
Memory Expansion: CXL enables FPGA-based systems to extend their memory capacity by connecting to CXL-compatible memory devices, improving performance in memory-bound applications like memory databases and large-scale data processing.
Data Processing: FPGAs with CXL support are used in data processing workloads, including real-time data analytics, financial modeling, and high-frequency trading, where low latency and high bandwidth are critical.

Fully integrated CXL IP solution with PCIe 5.0 x16 (32 GT/s) performance.
CXL 1.1 compliant IP that combines both hard and soft resources:
- R-Tile Hard IP (PHY IP) reduces logic resourcing and simplifies timing closure.
- Soft wrapper for added design flexibility and easy integration.
Validated with 4th and 5th Gen Intel® Xeon® Scalable Processors.
Compute Express Link Consortium compatible with CXL certification software (CXL_CV_app).
CXL protocol support: CXL.io, CXL.mem, CXL.cache.
Device type support: Type 1, 2, and 3.
CXL 1.1. IP enhanced with 2.0 features and functionality.
Flexible device-attached memory subsystem architecture:
- Allows FPGA developer to mix and manage different memory types for maximum scalability and application fit.