Security IP for TSMC
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- 16nm
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100G / 200G / 400G / 800G / 1.6T MACsec
- The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
- It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks.
- The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
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10M MACsec
- The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
- It protects components in Ethernet networks especially very low-speed Ethernet used in automotive, industrial, and consumer applications.
- The MACsec IP is a fully compliant solution that provides line-rate encryption and is optimized for the smallest area size.
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1G/2.5G/5G/10G/25G/50G MACsec
- The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
- It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure.
- The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
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3GPP Kasumi Accelerators
- Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
- Includes key scheduling hardware.
- Modes Kasumi
- Algorithms f8 and f9.
- Fully synchronous design.
- Low Speed, High Speed versions.
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Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
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RSA/ECC Public Key Accelerators with TRNG and AHB
- Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
- Public key signature generation, verification and key negotiation with little involvement of host
- NIST CAVP compliant for FIPS 140-3
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Small RSA/ECC Public Key Accelerators
- The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate count” deployment.
- Proven in silicon, the PKA-IP-28 public key accelerator addresses the unique needs of semiconductor OEMs and provides a reliable and cost-effective solution that is easy to integrate into SoC designs.
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ChaCha20 Accelerators
- The ChaCha-IP-13 (EIP-13) is an IP solution for accelerating the ChaCha20 cipher algorithm (RFC7539), supporting the NIST CTR mode up to 12.8 Gbps @ 300MHz.
- Designed for fast integration, low gate count and full transforms, the ChaCha-IP-13 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
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ARC4 Stream Cipher Accelerators
- The ARC4-IP-44 (EIP-44) is IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec) up to 5 Gbps @ 600MHz.
- Designed for fast integration, low gate count and full transforms, the ARC4-IP-44 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
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Poly1305 Crypto Accelerator
- Wide bus interface (128-bit data, 128-bit keys, 135-bit digest) or 32-bit register interface
- Key size: 128 bits
- Includes initialization stage
- Supports continuation mode
- Fully synchronous design
